A circuit board element includes a glass substrate, a first dielectric layer, and a first patterned metal layer. The glass substrate has an edge. The first dielectric layer is disposed on the glass substrate and has a central region and an edge region. The edge region is in contact with the edge of the glass substrate, and the thickness of the central region is greater than the thickness of the edge region. The first patterned metal layer is disposed on the glass substrate and in the central region of the first dielectric layer.

Graphene ink compositions comprising nitrocellulose and related methods of use comprising either thermal or photonic annealing.

Solid state lights (SSLs) including a back-to-back solid state emitters (SSEs) and associated methods are disclosed herein. In various embodiments, an SSL can include a carrier substrate having a first surface and a second surface different from the first surface. First and second through substrate interconnects (TSIs) can extend from the first surface of the carrier substrate to the second surface. The SSL can further include a first and a second SSE, each having a front side and a back side opposite the front side. The back side of the first SSE faces the first surface of the carrier substrate and the first SSE is electrically coupled to the first and second TSIs. The back side of the second SSE faces the second surface of the carrier substrate and the second SSE is electrically coupled to the first and second TSIs.

A power electronic assembly includes a board having metal layers laminated onto or between electrically insulating layers, and a laminate inlay embedded in the board. A first metal layer provides electrical contacts at a first side of the board. A second metal layer provides a thermal contact at a second side of the board. A third metal layer is positioned between the first metal layer and the laminate inlay and configured to distribute a load current switched by the laminate inlay. A fourth metal layer is positioned between the second metal layer and the laminate inlay and configured as a primary thermal conduction path for heat generated by the laminate inlay during switching of the load current. A first electrically insulating layer separates the fourth metal layer from the second metal layer so that the fourth metal layer is electrically isolated from but thermally connected to the second metal layer.

A surface mountable coupler may include a monolithic base substrate having a first surface, a second surface, a length in an X-direction, and a width in a Y-direction that is perpendicular to the X-direction. A plurality of ports may be formed over the first surface of the monolithic base substrate including a coupling port, an input port, and an output port. The coupler may include a first thin film inductor and a second thin film inductor that is inductively coupled with the first thin film inductor and electrically connected between the input and output ports. A thin film circuit may electrically connect the first thin film inductor with the coupling port. The thin film circuit may include at least one thin film component.

A printed circuit board including a dielectric insulation layer having a top side facing a first side and a bottom side opposite the first side that faces a second side of the dielectric insulation layer, at least one conducting track formed on the dielectric insulation layer, and one or more conductor rails, wherein each of the one or more conductor rails is mechanically coupled to the dielectric insulation layer, and a first portion of each of the one or more conductor rails is arranged on the first side and a second portion of each of the one or more conductor rails is arranged on the second side of the dielectric insulation layer.

A backplane and a glass-based circuit board. The backplane includes: a base substrate and a plurality of light-emitting units, arranged in an array on the base substrate. Each of the light-emitting units includes at least one light-emitting sub-unit; the light-emitting sub-unit includes a connection line and a plurality of light-emitting diode chips connected with the connection line, and the light-emitting diode chips are located on a side of the connection line away from the base substrate. The connection line comprises a first connection portion, a second connection portion and a third connection portion; in each of the light-emitting sub-units, the third connection portion comprises a plurality of connection sub-portions, each of the connection sub-portions comprise at least one electrical contact point; the electrical contact points at adjacent ends of adjacent connection sub-portions constitute an electrical contact point pair.

An electronic component housing package includes an insulating substrate including a first surface with a mounting region mounting an electronic component, a second surface located opposite to the first surface, a plurality of side surfaces located between the first surface and the second surface, and a corner portion located between two of the side surfaces; an external connection conductor located on the second surface; and a corner conductor connected to the external connection conductor. The corner conductor is located from the external connection conductor toward the corner portion in a manner to increase the distance from the second surface.

A method for manufacturing an aluminum circuit board including a step of spraying a heated metal powder containing aluminum particles and/or aluminum alloy particles to a ceramic base material, and of forming a metal layer on a surface of the ceramic base material. A temperature of at least a part of the metal powder is higher than or equal to a softening temperature of the metal powder and lower than or equal to a melting point of the metal powder at a time point of reaching the surface of the ceramic base material. A velocity of at least a part of the metal powder is greater than or equal to 450 m/s and less than or equal to 1000 m/s at the time point of reaching the surface of the ceramic base material.

A multilayer ceramic capacitor (MLCC) includes a body including first dielectric layers and second dielectric layers, the body including first to sixth surfaces, a second surface, a third surface, a fourth surface, a fifth surface and a sixth surface; first internal electrodes disposed on the first dielectric layers, exposed to the third surface, the fifth surface, and the sixth surface, and spaced apart from the fourth surface by first spaces; second internal electrodes disposed on the second dielectric layers to oppose the first internal electrodes with the first dielectric layers or the second dielectric layers interposed therebetween, exposed to the fourth surface, the fifth surface, and the sixth surface, and spaced apart from the third surface by second spaces; first dielectric patterns disposed in at least a portion of the first spaces, and second dielectric patterns disposed in at least a portion of the second spaces; and lateral insulating layers.