A ceramic circuit substrate having high bonding performance and excellent thermal cycling resistance properties, wherein a ceramic substrate and a copper plate are bonded by a braze material containing Ag and Cu, at least one active metal component selected from Ti and Zr, and at least one element selected from among In, Zn, Cd, and Sn, wherein a braze material layer, after bonding, has a continuity ratio of 80% or higher and a Vickers hardness of 60 to 85 Hv.

A substrate for mounting electronic element includes: a first substrate including a first surface and a second surface opposite to the first surface; a second substrate including a third surface and a fourth surface opposite to the third surface; and heat dissipation bodies each including a fifth surface and a sixth surface opposite to the fifth surface. The first substrate includes at least one mounting portion for at least one electronic element at the first surface. Heat conduction of the heat dissipation bodies in a direction perpendicular to a longitudinal direction of the at least one mounting portion and perpendicular to a direction along opposite sides of the second substrate is greater than heat conduction of the heat dissipation bodies in the longitudinal direction of the at least one mounting portion and in the direction along opposite sides of the second substrate in a transparent plan view of the substrate.

A carrier substrate (1) for electrical components, in particular metal-ceramic substrate (1) for electrical components, comprising an insulation layer (10), the insulation layer (10) preferably having a material comprising a ceramic or a composite comprising at least one ceramic layer, a component metallization (20) which is formed on a component side (BS) and has a first primary structuring (21), and a cooling part metallization (30) which is formed on a cooling side (KS) opposite the component side (BS) and has a second primary structuring (31), wherein the insulation layer (10), the component metallization (20) and the cooling part metallization (30) are arranged one above the other along a stacking direction (S), and
wherein the first primary structuring (21) and the second primary structuring (31), as viewed in the stacking direction (S), run congruently at least in portions.

According to the present invention, there is provided a copper/ceramic bonded body including: a copper member made of copper or a copper alloy; and a ceramic member made of silicon-containing ceramics, the copper member and the ceramic member being bonded to each other, in which a maximum indentation hardness in a region is set to be in a range of 70 mgf/μm.sup.2 or more and 150 mgf/μm.sup.2 or less, the region being from 10 μm to 50 μm with reference to a bonded interface between the copper member and the ceramic member toward the copper member side.

A ceramic substrate according to the present invention includes: a ceramic base material; an electrode pattern formed on the ceramic base material; and at least one spacer arranged in any one of regions in the ceramic base material and the electrode pattern, in which a semiconductor chip is mounted.

A method of forming a conductive pattern includes forming a conductive pattern by ejecting a liquid-state material containing conductive fine particles onto a porous base material, wherein the conductive fine particles have an average particle size of from 1 nm to 200 nm, and the porous base material is formed with a plurality of cavities and includes communication holes through which the plurality of cavities are in communication, an average diameter of the communication holes being less than or equal to the average particle size of the conductive fine particles.

Back plates to support integrated circuit packages in sockets on printed circuit boards and associated methods are disclosed. An example back plate includes a ceramic substrate having a first surface and a second surface opposite the first surface. The example back plate further includes metal coupled to the ceramic substrate. At least a portion of the metal is disposed between planes defined by the first and second surfaces of the ceramic substrate.

A multi-layer coating on an outer surface of a substrate includes a first layer applied directly to the outer surface of the substrate. The first layer includes diamond-like carbon (DLC) configured to mitigate metal whisker formation. A second layer is applied on a top surface of the first layer. The second layer is a conformal coating that includes a second material configured to bind to the top surface of the first layer and fill any microfractures that may form in the first layer. Optionally, a third layer is applied on a top surface of the second layer and includes DLC configured to protect the second layer from oxidation and degradation.

A circuit board 1 including: a substrate; an electrode pad on a surface of the substrate; and a projecting electrode on the electrode pad, wherein the electrode pad on which the projecting electrode is disposed is larger than the projecting electrode when viewed from above, and a coating layer covers at least a portion of an outer periphery of the electrode pad on which the projecting electrode is disposed.

A sintered body includes a crystal grain containing silicon nitride, and a grain boundary phase. If dielectric losses of the sintered body are measured while applying an alternating voltage to the sintered body and continuously changing a frequency of the alternating voltage from 50 Hz to 1 MHz, an average value ε.sub.A of dielectric losses of the sintered body in a frequency band from 800 kHz to 1 MHz and an average value ε.sub.B of dielectric losses of the sintered body in a frequency band from 100 Hz to 200 Hz satisfy an expression |ε.sub.A−ε.sub.B|≤0.1.