An electronic circuit, comprising: an integrated substrate structure comprising one or more electrically conductive traces comprising plating on a laser-etched, non-conductive isolated portion of the integrated substrate structure defining each electrically conductive trace; one or more electrically conductive pads at one or more predetermined positions along the one or more electrically conductive traces; and an electrical component surface mounted to the at least one electrically conductive pad with interconnect and bonding material.

An electronic circuit, comprising: an integrated substrate structure comprising one or more electrically conductive traces comprising plating on a laser-etched, non-conductive isolated portion of the integrated substrate structure defining each electrically conductive trace; one or more electrically conductive pads at one or more predetermined positions along the one or more electrically conductive traces; and an electrical component surface mounted to the at least one electrically conductive pad with interconnect and bonding material.

A circuit board includes a metal substrate, a resin layer, an insulating layer, and a first conductive structure. The metal substrate has a first through hole, and the first through hole has a first width. A portion of the resin layer is disposed in the first through hole. The resin layer has a second through hole. The second through hole has a second width. The insulating layer is disposed on at least one surface of the metal substrate, and a portion of the insulating layer contacts the resin layer. The first conductive structure is disposed in the second through hole. The first conductive structure penetrates through the metal substrate. The first width is greater than the second width. A manufacturing method of the circuit board is also provided.

A circuit board includes a metal substrate, a resin layer, an insulating layer, and a first conductive structure. The metal substrate has a first through hole, and the first through hole has a first width. A portion of the resin layer is disposed in the first through hole. The resin layer has a second through hole. The second through hole has a second width. The insulating layer is disposed on at least one surface of the metal substrate, and a portion of the insulating layer contacts the resin layer. The first conductive structure is disposed in the second through hole. The first conductive structure penetrates through the metal substrate. The first width is greater than the second width. A manufacturing method of the circuit board is also provided.

A lighting device includes a substrate having a plurality of flat portions and a non-flat portion disposed between the flat portions, a plurality of light emitting sources disposed on the substrate, a fluorescent substrate layer covering one or more light emitting sources and converting a wavelength of a light from the light emitting source, and a connection line disposed on the substrate and electrically connecting the light emitting sources adjacent to each other between the adjacent light emitting sources. The substrate has a first end and a second end are arranged at different distance from a central axis.

An antenna module comprises: a circuit board, having a three-dimensional keep-out area; an antenna, disposed on the circuit board and located in the keep-out area; and a metal piece, disposed on the circuit board and located in the keep-out area, wherein the metal piece is electrically insulated from the antenna.

An antenna module comprises: a circuit board, having a three-dimensional keep-out area; an antenna, disposed on the circuit board and located in the keep-out area; and a metal piece, disposed on the circuit board and located in the keep-out area, wherein the metal piece is electrically insulated from the antenna.

A circuit board heat sink structure having a circuit board and comprising a metallic heat sink, wherein the circuit board has a metal substrate, an insulation layer and a conductor layer, and the wherein the circuit board is arranged on the heat sink in such a way that the metal substrate contacts a locating face of the heat sink. At least one heat transition point is formed between the heat sink and the metal substrate, which provides a defined metallic contact between the material of the heat sink and the material of the metal substrate. A method is also provided for forming the circuit board heat sink structure.

A semiconductor device including a semiconductor chip disposed on a substrate having a conductive pattern, an insulating plate and a metal plate that are sequentially formed and respectively have the thicknesses of T2, T1 and T3. The metal plate has a plurality of depressions formed on a rear surface thereof. In a side view, a first edge face, which is an edge face of the conductive pattern, is at a first distance away from a second edge face that is an edge face of the metal plate, and a third edge face, which is an edge face of the semiconductor chip, is at a second distance away from the second edge face. Each depression is located within a depression formation distance from the first edge face, where: 0<depression formation distance≤(0.9×T1.sup.2/first distance), and/or (1.1×T1.sup.2/first distance)≤depression formation distance<second distance.

The present disclosure is directed to a hybrid conductive ink including: silver nanoparticles and eutectic low melting point alloy particles, wherein a weight ratio of the eutectic low melting point alloy particles and the silver nanoparticles ranges from 1:20 to 1:5. Also provided herein are methods of forming an interconnect including a) depositing a hybrid conductive ink on a conductive element positioned on a substrate, wherein the hybrid conductive ink comprises silver nanoparticles and eutectic low melting point alloy particles, the eutectic low melting point alloy particles and the silver nanoparticles being in a weight ratio from about 1:20 to about 1:5; b) placing an electronic component onto the hybrid conductive ink; c) heating the substrate, conductive element, hybrid conductive ink and electronic component to a temperature sufficient i) to anneal the silver nanoparticles in the hybrid conductive ink and ii) to melt the low melting point eutectic alloy particles, wherein the melted low melting point eutectic alloy flows to occupy spaces between the annealed silver nanoparticles, d) allowing the melted low melting point eutectic alloy of the hybrid conductive ink to harden and fuse to the electronic component and the conductive element, thereby forming an interconnect. Electrical circuits including conductive traces and, optionally, interconnects formed with the hybrid conductive ink are also provided.