H05K3/045

ARRAYED EMBEDDED MAGNETIC COMPONENTS AND METHODS
20190006077 · 2019-01-03 ·

Disclosed are apparatus and methods for arrayed embedded magnetic components that include magnetic devices that have a core that is embedded between two or more substrates and a winding pattern surrounding the core that is implemented on and through the two or more substrates. The winding pattern is operable to induce a magnetic flux within the core when energized by a time varying voltage potential. The winding pattern may be implemented by printed circuit layers, plated vias, other electrically conductive elements, and combinations thereof. Arrayed embedded magnetic components include two or more electrically interconnected magnetic devices positioned side-by-side in a horizontal integration, positioned top-to-bottom in a vertical integration, or combinations thereof. The magnetic devices may have a magnetic functionality such as, but not limited to, a transformer, inductor, and filter. Disclosed magnetic components and methods provide for low cost construction, consistent performance, and a low profile form, among other benefits.

MOUNTING COMPONENT, WIRING SUBSTRATE, ELECTRONIC DEVICE AND MANUFACTURING METHOD THEREOF

Disclosed is a wiring substrate including: a first wiring layer, a second wiring layer disposed on the first wiring layer interposed by an insulating film, and a via conductor passing through the insulating film in a thickness direction, the via conductor electrically connecting the first wiring layer and the second wiring layer. The second wiring layer and the via conductor include a second sintered metal layer and a first sintered metal layer arranged to surround the second sintered metal layer, and an average particle diameter of first metal particles forming the first sintered metal layer is smaller than an average particle diameter of second metal particles forming the second sintered metal layer.

PACKAGE SUBSTRATE
20180235085 · 2018-08-16 ·

A package substrate includes a dielectric layer, a first circuit layer, a second circuit layer and at least one electrically conductive pole. The dielectric layer includes a first side and a second side opposite to the first side. The first circuit layer is located at the first side of the dielectric layer, and includes a plurality of spaced first circuit patterns embedded into the dielectric layer. The second circuit layer is located at the second side of the dielectric layer, and includes a plurality of spaced second circuit patterns located on the second side the dielectric layer. The electrically conductive pole electrically couples the first circuit layer to the second circuit layer. Each of the first circuit patterns has an extension direction from the first side toward the second side, and has widths gradually decreasing along the extension direction.

Arrayed embedded magnetic components and methods
10049803 · 2018-08-14 · ·

Disclosed are apparatus and methods for arrayed embedded magnetic components that include magnetic devices that have a core that is embedded between two or more substrates and a winding pattern surrounding the core that is implemented on and through the two or more substrates. The winding pattern is operable to induce a magnetic flux within the core when energized by a time varying voltage potential. The winding pattern may be implemented by printed circuit layers, plated vias, other electrically conductive elements, and combinations thereof. Arrayed embedded magnetic components include two or more electrically interconnected magnetic devices positioned side-by-side in a horizontal integration, positioned top-to-bottom in a vertical integration, or combinations thereof. The magnetic devices may have a magnetic functionality such as, but not limited to, a transformer, inductor, and filter. Disclosed magnetic components and methods provide for low cost construction, consistent performance, and a low profile form, among other benefits.

Vehicular panel and wiring structure for vehicle

An instrument panel as a vehicular panel includes a panel body on a surface side of which key tops are installed, a printed wiring section arranged on the surface side of the panel body, and an insulation outer layer arranged on the surface side of the panel body so as to cover the printed wiring section.

Method of manufacturing a package substrate

A circuit board includes a dielectric layer, a first circuit layer, a second circuit layer and at least an electrically conductive pole. The dielectric layer includes a first side and a second side opposite to the first side. The first circuit layer is located at the first side of the dielectric layer, and includes a plurality of spaced first circuit patterns embedded into the dielectric layer. The second circuit layer is located at the second side of the dielectric layer, and includes a plurality of spaced second circuit patterns located outsides the dielectric layer. The electrically conductive pole electrically couples the first circuit layer to the second circuit layer. Each of the first circuit patterns has an extension direction from the first side toward the second side, and has widths thereof gradually decreasing along the extension direction. A method for manufacturing the circuit board is also provided.

MANUFACTURING METHOD FOR WIRING BOARD
20180103547 · 2018-04-12 ·

A method for manufacturing a wiring board that has a rewiring layer on a surface thereof includes forming an insulating layer on a core substrate, forming a groove, in which a wiring layer of a circuit pattern is to be provided, on the insulating layer, forming a metal seed layer on an exposed face of the insulating layer on which the groove is formed, electrodepositing metal, which is to form the wiring layer, by plating to fill the groove with the metal to form a metal layer on the seed layer, machining the metal layer by a cutting tool to remove the metal layer up to a position not reaching the top of the insulating layer, and performing etching or a CMP process to expose the top of the insulating layer thereby to form the wiring layer in the groove and flatten an exposed face of the wiring layer.

CHIP PART AND MANUFACTURING METHOD THEREOF

A chip part includes a substrate having a first main surface on one side thereof and a second main surface on the other side thereof, a functional device famed at a first main surface side of the substrate, an external terminal formed at the first main surface side of the substrate and electrically connected to the functional device, and a light diffusion reflection structure formed at a second main surface side of the substrate and diffusely reflecting light irradiated toward the second main surface of the substrate.

Embedded magnetic components and methods
09754712 · 2017-09-05 · ·

Disclosed are apparatus and methods for a magnetic component. In accordance with an embodiment, a magnetic component comprises a base substrate defining a winding cup having a shape of a closed groove surrounding a hub. The winding cup defines a core space operable to receive a core therein. A first conductive pattern is disposed on at least a portion of the base substrate including the winding cup. A second substrate defines a second conductive pattern. The second substrate is coupled to the first base surface with the first conductive pattern in operable alignment with the second conductive pattern. The first and second conductive patterns are coupled in electrical communication so as to define one or more winding-type electric circuits surrounding the core space so as to induce a magnetic flux within the core space when the one or more electric circuits are energized by a voltage source.

EMBEDED CIRCUIT PATTERNING FEATURE SELECTIVE ELECTROLESS COPPER PLATING

Embodiments describe the selective electroless plating of dielectric layers. According to an embodiment, a dielectric layer is patterned to form one or more patterned surfaces. A seed layer is then selectively formed along the patterned surfaces of the dielectric layer. An electroless plating process is used to deposit metal only on the patterned surfaces of the dielectric layer. According to an embodiment, the dielectric layer is doped with an activator precursor. Laser assisted local activation is performed on the patterned surfaces of the dielectric layer in order to selectively form a seed layer only on the patterned surfaces of the dielectric layer by reducing the activator precursor to an oxidation state of zero. According to an additional embodiment, a seed layer is selectively formed on the patterned surfaces of the dielectric layer with a colloidal or ionic seeding solution.