Patent classifications
H05K3/243
PRINTED WIRING BOARD
A printed wiring board includes an insulating sheet, a conductive layer formed on one main surface of the insulating sheet, and an insulating film laminated with an adhesive layer on the main surface of the insulating sheet formed with the conductive layer. The position of an end part of the insulating film is located outside the position of an end part of the adhesive layer.
PRINTED WIRING BOARD
A printed wiring board includes a first resin insulating layer, a conductor layer on the first resin insulating layer, and a second resin insulating layer formed on the first resin insulating layer such that the second resin insulating layer is covering the conductor layer. The conductor layer includes a first circuit having a width of 15 μm or less and a rectangular cross-sectional shape, a second circuit having a trapezoidal cross-sectional shape, a third circuit, a fourth circuit, a fifth circuit, and a sixth circuit, a space between the first and third circuits has a width of 14 μm or less, a space between the first and fourth circuits has a width of 14 μm or less, a space between the second and fifth circuits has a width of 20 μm or more, and a space between the second and sixth circuits has a width of 20 μm or more.
Flexible circuit board and method for producing same
The present invention comprises: a base film on which a first element mounting part and a second element mounting part are defined; wiring patterns formed by extending from each of the first element mounting part and the second element mounting part on the base film, wherein the wiring patterns include a first terminal part in the first element mounting part and a second terminal part in the second element mounting part; and a first plating layer formed on the second terminal part, wherein the first plating layer includes a pure metal plating layer, and the first plating layer is not formed on the first terminal part.
MASK FOR PARTIAL PLATING, AND METHOD FOR PRODUCING INSULATED CIRCUIT BOARD AND PARTIAL PLATING METHOD USING THE MASK
A mask for partial plating capable of performing partial electroplating selectively on a prescribed portion on a surface of an electrically isolated metal member provided on an insulated board is provided. Methods for producing an insulated circuit board and using the mask for partial plating are also provided. The mask for partial plating includes an insulated sheet member having an opening corresponding to the portion to be plated, and a structure including a partial region on one surface in the thickness direction of the insulated sheet member being coated with one or plural conductive sheet members attached to the region. The conductive sheet member is adhered to the surface of the insulated sheet member, for example, with an adhesive or an adhesive member. The conductive sheet member may be engaged in a recessed portion formed on the surface of the insulated sheet member.
Method of fabricating contact pads for electronic substrates
Electronic substrates, contact pads for electronic substrates, and related methods are disclosed. Electronic substrates may include an electrically conductive layer that forms at least one contact pad and at least one metal trace on a non-conductive layer. The contact pads are arranged with greater thicknesses or heights above the non-conductive layer than the metal traces. Dielectric layers are disclosed that cover the metal traces while leaving top surfaces of the contact pads exposed. Top surfaces of the dielectric layers may be arranged to be coplanar with top surfaces of the contact pads to provide electronic substrates having generally planar top faces. Bottom faces of electronic substrates may include mounting pads that are coplanar with additional dielectric layers. Methods are disclosed that include forming dielectric layers to cover contact pads and metal traces, and removing surface portions of the dielectric layers until the contact pads are accessible through the dielectric layers.
Method for producing insulated circuit board using a mask and partial plating method using the mask
A mask for partial plating capable of performing partial electroplating selectively on a prescribed portion on a surface of an electrically isolated metal member provided on an insulated board is provided. Methods for producing an insulated circuit board and using the mask for partial plating are also provided. The mask for partial plating includes an insulated sheet member having an opening corresponding to the portion to be plated, and a structure including a partial region on one surface in the thickness direction of the insulated sheet member being coated with one or plural conductive sheet members attached to the region. The conductive sheet member is adhered to the surface of the insulated sheet member, for example, with an adhesive or an adhesive member. The conductive sheet member may be engaged in a recessed portion formed on the surface of the insulated sheet member.
Machining Station and Method for Machining Workpieces
The disclosure relates to a machining station for machining platelike workpieces (1) by means of at least one tool (10, 13, 14). The machining station has a measuring device (16) for acquiring data relating to the position of bores, a drill (10, 13, 14) for generating bores in the workpiece (1), and a data processor (17) for processing data of the at least one measuring device (16) and/or for controlling the at least one drill (10, 13, 14). The data processor (17) is here suitable and set up for performing an adjustment between a desired drilling position and/or a desired bore depth and an actual position and/or actual depth as determined by the at least one measuring device (16) for a bore present in the workpiece (1), and adapting the drilling position and/or bore depth for generating bores by means of the at least one drill (10, 13, 14).
Electrical devices and methods of manufacture
A die can be applied to a front conductive layer. Openings can be formed in the conductive layer over contact points on the die. The openings can be filled with a conductive material to electrically couple the conductive layer to the contact points on the die. The front conductive layer can be etched to form a first conductive pattern. Conductive standoffs can be formed on portions of the front conductive layer. An additional front conductive layer can be laminated onto the front side. Openings can be formed in the additional front conductive layer over the standoffs. The openings can be filled with a conductive material to electrically couple the additional conductive layer to the underlying standoffs. The additional conductive layer can be etched to form a second conductive pattern.
VERTICAL POWER SUPPLY SYSTEM AND MANUFACTURING METHOD OF CONNECTION BOARD
A vertical power supply system and a manufacturing method of a connection board are provided. The vertical power supply system includes a system board, a substrate, a chip unit, a plurality of first capacitors, a plurality of second capacitors, a plurality of conductive portions and a power unit. The system board includes a first surface and a second surface which are opposite to each other. The substrate includes a third surface and a fourth surface which are opposite to each other, and the third surface is located between the fourth surface and the second surface. The chip unit is disposed on the first surface. The first capacitors are disposed on the second surface. The second capacitors are disposed on the third surface. The third surface and the second surface are electrically connected through the conductive portions. The power unit is disposed on the fourth surface.
Substrate bonding pad having a multi-surface trace interface
A bonding pad such as for a ball grid array includes a conductive pad having a top surface and a first interface surface in contact with a signal trace of a substrate, and a plating layer having a bottom surface in direct contact with the top surface of the conductive pad. The plating layer includes one or more protrusions extending toward the signal trace in a direction generally parallel to a longitudinal axis of the signal trace. Each of the one or more protrusions includes two parallel sidewalls extending upwardly from the bottom surface of the plating layer, and a second interface surface contiguous with the bottom surface of the plating layer. The second interface surface is positioned over and in direct contact with a top surface of the signal trace. The protrusions prevent the connection to the signal trace from being compromised.