A wiring board (10) includes a substrate (11) and a mesh wiring layer (20) disposed on the substrate (11) and including a plurality of wiring lines (21, 22). The substrate (11) has a transmittance of 85% or more for light with a wavelength of 380 nm or more and 750 nm or less. Each of the wiring lines (21, 22) includes a metal layer (27) and a blackened layer (28) disposed on the metal layer (27). The blackened layer (28) has a thickness (T.sub.2) of 5 nm or more and 100 nm or less.

A printed circuit board includes an insulating layer, a circuit pattern on the insulating layer, and a surface treatment layer on the circuit pattern. The surface treatment layer includes a bottom surface having a width wider than a width of a top surface of the circuit pattern.

Electronic substrates, contact pads for electronic substrates, and related methods are disclosed. Electronic substrates may include an electrically conductive layer that forms at least one contact pad and at least one metal trace on a non-conductive layer. The contact pads are arranged with greater thicknesses or heights above the non-conductive layer than the metal traces. Dielectric layers are disclosed that cover the metal traces while leaving top surfaces of the contact pads exposed. Top surfaces of the dielectric layers may be arranged to be coplanar with top surfaces of the contact pads to provide electronic substrates having generally planar top faces. Bottom faces of electronic substrates may include mounting pads that are coplanar with additional dielectric layers. Methods are disclosed that include forming dielectric layers to cover contact pads and metal traces, and removing surface portions of the dielectric layers until the contact pads are accessible through the dielectric layers.

Devices and methods are described for reducing etching due to galvanic effect within a printed circuit board that may be used, for example, in a data storage device, such as a card-type data storage device. Specifically, a contact trace is coupled to a contact finger that has a substantially larger surface area than the contact trance, and that is configured to couple the data storage device to a host device. The contact trace is electrically isolated from the rest of the circuitry during a fabrication process. The contact finger and an exposed portion of the contact trace are plated with a common material to reduce galvanic etching of the contact trace during fabrication. The contact trace is then connected to an impedance trace though at least one of a component and a bond wire.

A high-speed transmission circuit comprises a connector pin that serves as part of a signal path, has a first conductivity, and has a connector pin leg that is coupled to a pad that has a second conductivity lower than the first conductivity. The connector pin leg and at least a portion of the pad form a resonant sub-circuit coupled to the signal path. The second conductivity causes a reduction in insertion loss in the signal path by damping a current in the resonant sub-circuit.

A printed wiring board includes a resin insulating layer, a metal post formed in the resin insulating layer such that the metal post is protruding from a first surface of the resin insulating layer, a conductor layer formed on a second surface of the resin insulating layer on the opposite side with respect to the first surface of the resin insulating layer, and a via conductor formed in the resin insulating layer such that the via conductor is penetrating through the resin insulating layer and connecting the metal post and the conductor layer. The metal post has a protruding portion protruding from the first surface of the resin insulating layer and an embedded portion integrally formed with the protruding portion and embedded in the resin insulating layer.

A second wiring layer is connected to a first wiring layer via an insulating layer. The second wiring layer comprises pad structures. Each pad structure includes a first metal layer formed on the insulating layer, a second metal layer formed on the first metal layer, and a third metal layer formed on the second metal layer. The pad structures comprises a first pad structure and a second pad structure. A via-wiring diameter of the first pad structure is different from a via-wiring diameter of the second pad structure. A distance from an upper surface of the insulating layer to an upper surface of the second metal layer of the first pad structure is the same as a distance from the upper surface of the insulating layer to an upper surface of the second metal layer of the second pad structure.

A circuit board including a substrate, a patterned conductive layer, a patterned insulating layer, a conductive terminal, and a dummy terminal is provided. The patterned conductive layer is disposed on the substrate. The patterned insulating layer is disposed on the substrate and at least covers a portion of the patterned conductive layer. The conductive terminal is disposed on the patterned conductive layer and has a first top surface. The dummy terminal is disposed on the patterned conductive layer and has a second top surface. A first height between the first top surface and the substrate is greater than a second height between the second top surface and the substrate.

The present invention is directed to a composition for depositing a palladium coating on a substrate, in particular on a nickel-coated substrate, the composition comprising: (i) palladium ions, (ii) chloride ions, (iii) ethylenediamine (EDA), (iv) ethylenediamine disuccinate (EDDS), and (v) at least one reducing agent.

Embodiments and fabrication methods for a printed circuit board comprising two or more electrically conductive layers, including at least a first conductive layer opposing and adjacent to a second conductive layer. Also including one or more electrically non-conductive layers including at least a first non-conductive layer disposed between the first conductive layer and the second conductive layer. A first copper pad is included on the first conductive layer. A second copper pad is included on the second conductive layer. There is a conductive via extending through the first non-conductive layer and electrically connecting the first copper pad to the second copper pad and solder mask material on the first copper pad around the via.