The disclosure relates to a method for manufacturing a transfer film including an electrode layer, the method comprising: an electrode layer formation step of forming an electrode layer on a carrier member by using a conductive material; a placement step of placing the carrier member on at least one side of an insulating resin layer respectively; a bonding step of bonding the carrier member and the insulating resin layer together by applying pressure thereto; and a transfer step of removing the carrier member to transfer the electrode layer on the insulating resin layer.

A coupled via structure includes a plate via penetrating through an board body and having first and second plates spaced apart from each other by a first gap distance, a contact pad connected to the plate via on a surface of the board body and having first and second contacts connected to the first and second plates, respectively, and a connection line connected to the contact pad on the surface of the board body and having first and second lines connected to the first and second contacts, respectively, and spaced apart from the first line by a second gap distance. Accordingly, the deviation of the characteristic impedance is reduced (or, alternatively, minimized) between the coupled via structure and the coupled signal line.

A memory card comprising a first main surface and a second main surface opposing each other, and including a printed circuit board (PCB) constituting the first main surface, the PCB including a plurality of first external connection terminals, the plurality of first external connection terminals exposed on the first main surface, a plurality of memory devices stacked on the PCB, a memory controller configured to control the plurality of memory devices, a molding layer encapsulating the plurality of memory devices and the memory controller, the molding layer constituting the second main surface, and one or more second external connection terminals electrically connected to the memory controller, the one or more second external connection terminals embedded in the molding layer and exposed by the molding layer on the second main surface may be provided.

A circuit board is formed from a non-catalytic laminate coated with an optically curable catalytic adhesive, which, after curing with an optical source such as UV, has a resin rich surface with catalytic particles dispersed below a surface exclusion depth. The catalytic laminate is subjected to a drilling and blanket surface plasma etch operation to expose the catalytic particles, followed by an electroless plating operation which deposits a thin layer of conductive material on the surface. A photo-masking step follows to define circuit traces, after which an electro-plating deposition occurs, followed by a resist strip operation and a quick etch to remove electroless copper which was previously covered by photoresist.

The present invention relates to methods and systems for deposition of metal conductors using asymmetrical electrolytic plating, in which one surface (e.g., top) of a substrate is coated with an electrical conductor, and an opposite (e.g., bottom, or other) surface of which is not coated. A channel is formed between the two sides of the substrate, passing through the substrate and, in some embodiments, passing through the conductor. Electrolytic plating is performed such that metal is deposited from the edge of the conduct proximal to the channel, along the side walls of the channel, and up to, and in some embodiments on to, the other side of the substrate. Use of etching or plate resist layers are also contemplated.

A circuit board according to an embodiment includes an insulating layer; and a via formed in the insulating layer; wherein a width of an upper surface of the via is greater than a width of a lower surface of the via, and wherein the width of the lower surface of the via is 75% to 95% of the width of the upper surface of the via.

A method of preparing a non-conductive substrate to allow metal plating thereon. The method includes the steps of a) contacting the non-conductive substrate with a conditioner comprising a conditioning agent; b) applying a carbon-based dispersion to the conditioned substrate, wherein the carbon-based dispersion comprises carbon or graphite particles dispersed in a liquid solution; and c) etching the non-conductive substrate. The etching step is performed before the liquid carbon-based dispersion dries on the non-conductive substrate.

The present invention relates to a leveling agent and an electrolytic composition comprising the same. When the via hole in the substrate is filled with the electrolytic composition according to the present invention, the via hole can be filled within a relatively short time while minimizing the formation of dimples or voids.

A multi-layer circuit board is formed by positioning a top sub having traces on at least one side to one or more pairs of composite layers, each composite layer comprising an interposer layer and a sub layer. Each sub layer which is adjacent to an interposer layer having an interconnection aperture, the interconnection aperture positioned adjacent to interconnections having a plated through via or pad on each corresponding sub layer. Each interposer aperture is filled with a conductive paste, and the stack of top sub and one or more pairs of composite layers are placed into a lamination press, the enclosure evacuated, and an elevated temperature and laminated pressure is applied until the conductive paste has melted, connecting the adjacent interconnections, and the boards are laminated together into completed laminated multi-layer circuit board.

An article includes a glass or glass-ceramic substrate having a first major surface and a second major surface opposite the first major surface, and at least one via extending through the substrate from the first major surface to the second major surface over an axial length in an axial dimension. The article also includes a metal connector disposed within the via that hermetically seals the via. The article has a helium hermeticity of less than or equal to 1.010.sup.8 atm-cc/s after 1000 thermal shock cycles, each of the thermal shock cycle comprises cooling the article to a temperature of 40 C. and heating the article to a temperature of 125 C., and the article has a helium hermeticity of less than or equal to 1.010.sup.8 atm-cc/s after 100 hours of HAST at a temperature of 130 C. and a relative humidity of 85%.