A printed wiring board includes a base insulating layer, a conductor layer formed on the base layer and including conductor pads, an underlayer formed on one of the conductor pads and including a metal different from a metal of the conductor layer, a solder resist layer formed on the base layer such that the solder resist layer is covering the conductor layer and has openings exposing the conductor pads, and a bump formed directly on a first conductor pad of the conductor pads and including a base plating layer formed in a first opening of the openings and a top plating layer formed on the base plating layer such that a metal of the base plating layer is same as the metal of the conductor layer. The conductor pads include a second conductor pad such that the second conductor pad is the one of the conductor pads having the underlayer.

An embedded PCB includes a first substrate, an electronic component mounted on the first substrate, a second substrate provided on a side opposite to the first substrate with the electronic component interposed therebetween, and electrically connected to the first substrate via substrate bonding members, and an encapsulating resin filled between the first and second substrates, covering the electronic component, and also filled between the electronic component and the first substrate. The first substrate includes, on a side closer to the electronic component, pads to be bonded to electrodes of the electronic component via bonding portions, and a protective insulating layer including openings. The pads include outermost peripheral pads in an outermost periphery including four corners of an approximately rectangular area in a plan view, and inner pads in an area surrounded by the outermost peripheral pads.

In an embodiment a carrier includes a base substrate, at least one insulating layer, at least one inner wiring layer, at least one outer wiring layer and at least one through-via in the insulating layer extending through the insulating layer, wherein the base substrate and the insulating layer are formed from different materials, wherein the base substrate is formed for mechanically stabilizing the carrier and supports the insulating layer, wherein the inner wiring layer is arranged in a vertical direction at least in places between the base substrate and the insulating layer, wherein the outer wiring layer is spatially separated from the inner wiring layer at least in places by the insulating layer, and wherein the through-via electrically conductively connects the inner wiring layer to the outer wiring layer and has a lateral cross-section having a maximum lateral extent of at most 100 μm.

A packaging substrate includes a core layer including a glass substrate with a first surface and a second surface facing each other, and a plurality of core vias. The plurality of core vias penetrating through the glass substrate in a thickness direction, each comprising a circular core via having a circular opening part and a non-circular core via having an aspect ratio of 2 to 25 in the x-y direction of an opening part. One or more electric power transmitting elements are disposed on the non-circular core via.

A printed wiring board includes a base insulating layer, a conductor layer formed on the base layer and including conductor pads, an underlayer formed on one of the conductor pads and including a metal different from a metal of the conductor layer, a solder resist layer formed on the base layer such that the solder resist layer is covering the conductor layer and has openings exposing the conductor pads, and a bump formed directly on a first conductor pad of the conductor pads and including a base plating layer formed in a first opening of the openings and a top plating layer formed on the base plating layer such that a metal of the base plating layer is same as the metal of the conductor layer. The conductor pads include a second conductor pad such that the second conductor pad is the one of the conductor pads having the underlayer.

A glass core device with a wiring pattern on a first surface of a glass core and a wiring pattern on a second surface thereof being electrically connected via a wiring pattern embedded in TGVs formed in the glass core. In a state of being cut out by dicing, each glass core has a second surface and side faces which are continuously covered with an outer protective layer.

A flip-chip package substrate and a method for fabricating the same are provided. An insulation layer is formed on two opposing sides of a middle layer to form a composite core structure and increase the rigidity of the flip-chip package substrate. Therefore, the core structure can be made thinner. The conductive structures can also have a smaller end size, and more conductive points can be disposed within a unit area. Therefore, a circuit structure can be produced that have a fine line pitch and a high wiring density, satisfy the packaging demands of highly integrated circuit/large size substrate, and avoid an electronic package from being warpage.

A package substrate that prevents breakage of a core substrate is provided. A package substrate includes a core substrate made of a brittle material, at least one insulating layer formed on one surface or both surfaces of the core substrate, and one or more wiring layers formed on the insulating layer and/or in the insulating layer, the core substrate being exposed from an outer peripheral portion of the insulating layer, and the insulating layer being chamfered.

A glass core, a multilayer circuit board, and a method of manufacturing a glass core that appropriately form copper wiring, and suppresses crack and the like, a glass core includes: a glass plate; a first metal layer provided on the glass plate; a first electrolytic copper plating layer provided on the first metal layer; a dielectric layer provided above the first electrolytic copper plating layer; a second metal layer provided on the dielectric layer; an electroless nickel plating layer provided on the second metal layer and having a phosphorus content of less than 5 mass %; and a second electrolytic copper plating layer provided on the electroless nickel plating layer.

A component carrier includes a stack having a first electrically insulating layer structure and a first electrically conductive layer structure arranged on the first electrically insulating layer structure. The first electrically insulating layer structure has at least one first covered portion, which is covered by the first electrically conductive layer structure, and at least one first non-covered portion, which is not covered by the first electrically conductive layer structure. The first electrically insulating layer structure defines a recess at the at least one first non-covered portion.