A ceramic electronic component that includes a plurality of ceramic layers which are stacked together, and an internal conductor layer disposed between two adjacent ceramic layers among the plurality of ceramic layers, and in which a ceramic layer that is adjacent to the internal conductor layer includes a plurality of pores.

A component carrier includes a stack having at least one electrically conductive layer structure and at least one electrically insulating layer structure; a barrier structure; and a component. The component has at least one pad embedded in the stack and/or in the barrier structure. At least a portion of one of the electrically conductive layer structure and the at least one pad includes copper in contact with the barrier structure.

An electronics package is disclosed. The electronics package includes a first radio frequency (RF) substrate layer, a second RF substrate layer, and a plurality of conductive layers disposed adjacent to at least one of the first RF substrate layer and the second RF substrate layer and including an inner conductive layer disposed between and adjacent to both the first RF substrate layer and the second RF substrate layer. The inner conductive layer bonds the first RF substrate layer to the second RF substrate layer. The electronics package also includes a plurality of conductive interconnects extending through the first RF substrate layer and the second RF substrate layer and electrically coupled between at least two of the plurality of conductive layers.

An inductor built-in substrate includes a core substrate having an opening and a first through hole formed therein, a magnetic resin filling the opening formed in the core substrate such that the magnetic resin has second through holes formed therein, a first through-hole conductor formed in the first through hole of the core substrate and including a metal film formed in the first through hole of the core substrate, and second through-hole conductors formed in the second through holes of the magnetic resin and including metal films formed in the second through holes of the magnetic resin, respectively.

A circuit board has a glass core in which a through hole is formed, and a conductor pattern is formed on an inner peripheral wall of the through hole and a surface of the glass core to form a circuit element including a solenoid coil element and a capacitor element. Accordingly, a low-cost and compact circuit board capable of supporting high-capacity communication for thin mobile communication devices such as smartphones can be provided. Since the circuit board can be electrically connected to at least one of the electronic components such as a switch, an amplifier, and a filter via one terminal, and can be electrically connected to a mother board via another terminal, it has integrated functions, and can be suitably used for thin mobile communication devices such as smartphones.

A glass wiring board is provided with an analog duplexer including an inductor and a capacitor, and includes: a core wiring board provided with the coil-shaped inductor having through electrodes and wiring patterns provided in a glass substrate via an inorganic adhesive layer, and with a land pattern connected to an outer layer; the capacitor having a structure with a dielectric layer sandwiched between upper and lower electrode patterns on an insulating resin layer covering the core wiring board; and a wiring pattern for connecting to an external component such as an external substrate.

A flip-chip package substrate and a method for fabricating the same are provided. An insulation layer is formed on two opposing sides of a middle layer to form a composite core structure and increase the rigidity of the flip-chip package substrate. Therefore, the core structure can be made thinner. The conductive structures can also have a smaller end size, and more conductive points can be disposed within a unit area. Therefore, a circuit structure can be produced that have a fine line pitch and a high wiring density, satisfy the packaging demands of highly integrated circuit/large size substrate, and avoid an electronic package from being warpage.

A technique for making a glass core substrate that is less prone to cracking. A core substrate of the present invention includes a glass plate and a first conductor pattern provided on a first main surface of the glass plate. The first conductor pattern includes a first nickel plating layer that is provided on the first main surface of the glass plate and has a phosphorus content of 5 mass % or less and a first copper plating layer that is provided on the first nickel plating layer.

Techniques for mounting a semiconductor chip in a circuit board assembly includes using different buildup materials on opposite sides of a core to optimize stress in the first level interconnect structure (between the chip and core) and/or the second level interconnect structure (between the core and circuit board). The core can be, for example, ceramic, glass, or glass cloth-reinforced epoxy. In one example, the first side of the core has one or more layers of conductive material within a first buildup structure comprising a first buildup material. The second side of the substrate has one or more layers of conductive material within a second buildup structure comprising a second buildup material different from the first buildup material. In another example, an outermost layer of the second buildup structure is a ductile material that functions to decouple stress in the interconnect between the substrate and a circuit board.

A wiring substrate includes: a wiring structure that includes a wiring layer and an insulating layer laminated; a plurality of first posts that are formed along a periphery of a predetermined area on a surface of the wiring structure, and that protrude out from the surface of the wiring structure; and a second post that is connected to the wiring layer at a position surrounded by the first posts, and that protrudes out from the surface of the wiring structure. The first posts are formed such that a post arranged at a central portion of a side constituting the periphery of the predetermined area is lower in height from the surface of the wiring structure than posts arranged at both ends of the side.