This disclosure relates generally to an electronic chip package that can include a die and a buildup layer substantially enveloping the die. Electrical interconnects can be electrically coupled to the die and passing, at least in part, through the buildup layer. An optical emitter can be electrically coupled to the die with a first one of the electrical interconnects and configured to emit light from a first major surface of the electronic chip package. A solder bump can be electrically coupled to the die with a second one of the electrical interconnects and positioned on a second major surface of the electronic chip package different from the first major surface.

A conductor of the invention is in a form of a conductive convex portion in a laminated wiring member and includes a conductive material and a liquid repellent, in which the conductive material is in a form of metal particles, the liquid repellent is a fluorine-containing compound adapted to form a self-assembled monomolecular film. The conductor has a surface energy in a range from more than 30 mN/m to 80 mN/m. The conductor of the invention is exemplified by the conductive convex portion in the laminated wiring member and functions as a VIA post in the laminated wiring member.

A multilayer printed circuit board includes a first circuit board, a second circuit board and bonding films. The first circuit board includes a first dielectric layer, a first wiring pattern layer, a plurality of conductive blocks and a plurality of solder balls. The first wiring pattern layer is formed on a first surface of the first dielectric layer and the conductive blocks are formed on a second surface of the first dielectric layer. The solder balls are formed on a surface of the first wiring pattern layer. The second circuit board includes a second dielectric layer, a second wiring pattern layer, second conductive blocks and conductive pillars. The second wiring pattern layer is formed on a third surface of the second dielectric layer and the second conductive blocks are formed on a fourth surface thereof. The conductive pillars are formed on the second wiring pattern layer.

A packaging substrate includes a first dielectric layer, a first wiring layer, a first conductive pillar layer, a second dielectric layer, a second wiring layer, an electrical pad layer, and a third dielectric layer. The first dielectric layer has a first surface, a second surface opposite to the first surface, plural openings, and a wall surface that faces at least one of the openings. The first wiring layer is located on the first surface and the wall surface. A portion of the first wiring layer on an edge of the wall surface adjacent to the second surface extends in a direction away from the wall surface. The first conductive pillar layer is located on a portion of the first wiring layer. The second dielectric layer is located on the first surface, the first wiring layer, and in the openings.

A method of making a stackable wiring board is characterized by positioning an electronic component in a dielectric recess to realize the thickness reduction of the wiring board and sidewalls of the recess can confine the dislocation of the electronic component to avoid misalignment between buildup circuitry and the electronic component. A plurality of plated through holes are formed to provide vertical electrical connections between dual buildup circuitries, thereby providing the wiring board with stacking capability.

A manufacturing method of a double layer circuit board comprises forming at least one connecting pillar on a first circuit, wherein the at least one connecting pillar comprises a first end, connected to the first circuit, and a second end, opposite to the first end; forming a substrate on the first circuit and the at least one connecting pillar; drilling the substrate to expose a portion of the second end of the at least one connecting pillar, wherein the other portion of the second end of the at least one connecting pillar is covered by the substrate; and forming a second circuit on the substrate and the portion of the second end of the at least one connecting pillar, wherein an area of the first end connected to the first circuit layer is greater than an area of the portion of the second end connected to the second circuit layer.

A circuit board with a heat-recovery function includes a substrate, a heat-storing device, and a thermoelectric device. The heat-storing device is embedded in the substrate and connected to a processor for performing heat exchange with the processor. The thermoelectric device embedded in the substrate includes a first metal-junction surface and a second metal-junction surface. The first metal-junction surface is connected to the heat-storing device for performing heat exchange with the heat-storing device. The second metal-junction surface is joined with the first metal-junction surface, in which the thermoelectric device generates an electric potential by a temperature difference between the first metal-junction surface and the second metal-junction surface.

A circuit board element includes a glass substrate, a first dielectric layer, and a first patterned metal layer. The glass substrate has an edge. The first dielectric layer is disposed on the glass substrate and has a central region and an edge region. The edge region is in contact with the edge of the glass substrate, and the thickness of the central region is greater than the thickness of the edge region. The first patterned metal layer is disposed on the glass substrate and in the central region of the first dielectric layer.

A circuit board element includes a glass substrate, a first dielectric layer, and a first patterned metal layer. The glass substrate has an edge. The first dielectric layer is disposed on the glass substrate and has a central region and an edge region. The edge region is in contact with the edge of the glass substrate, and the thickness of the central region is greater than the thickness of the edge region. The first patterned metal layer is disposed on the glass substrate and in the central region of the first dielectric layer.

A method of making a stackable wiring board is characterized by positioning an electronic component in a dielectric recess to realize the thickness reduction of the wiring board and sidewalls of the recess can confine the dislocation of the electronic component to avoid misalignment between buildup circuitry and the electronic component. An array of metal posts that provide vertical electrical connections are formed by using the same metal carrier that forms the recess, so that the predetermined distance and relative location between metal posts and pads/bumps of the electronic component can be maintained.