Disclosed are a printed circuit board and a method for manufacturing the same. The printed circuit board includes a core insulating layer, at least one via formed through the core insulating layer, an inner circuit layer buried in the core insulating layer, and an outer circuit layer on a top surface or a bottom surface of the core insulating layer. The via includes a first part, a second part below the first part, and a third part between the first and second parts, and the third part includes a metal different from a metal of the first and second parts. The inner circuit layer and the via are simultaneously formed.

A method of manufacturing an interposer substrate, including providing a carrier having a first circuit layer formed thereon, forming a plurality of conductive pillars on the first circuit layer, forming a first insulating layer on the carrier, with the conductive pillars being exposed from the first insulating layer, forming, on the conductive pillars a second circuit layer that is electrically connected to the conductive pillars, forming a second insulating layer on the second surface of the first insulating layer and the second circuit layer, exposing a portion of a surface of the second circuit layer from the second insulating layer, and removing the carrier. The invention further provides the interposer substrate as described above.

A printed circuit board and a method of manufacturing a printed circuit board are provided. The printed circuit board includes an insulating layer, a circuit layer embedded in the insulating layer, a solder resist layer disposed on one surface of the insulating layer, the solder resist layer having a cavity of a through-hole shape to expose a part of the circuit layer from the insulating layer, and a metal post embedded in the solder resist layer and exposed to outside via an opening of the solder resist layer, and the metal post includes a first post metal layer, a post barrier layer, and a second post metal layer disposed in that order.

A printed wiring board includes a central resin insulating layer, an electronic component embedded in the central resin insulating layer, a first resin insulating layer formed on a first surface side of the central resin insulating layer, and a second resin insulating layer formed on a second surface side of the central resin insulating layer on the opposite side with respect to the firs surface side. The central resin insulating layer does not contain a core material, and one of the first resin insulating layer and the second resin insulating layer includes a core material and the other one of the first resin insulating layer and the second resin insulating layer does not contain a core material.

The embodiments of the invention disclose a touch screen, a method for producing a touch screen, and a touch display device, which relate to a field of display. The touch screen does not need bridging, have high transmittance, and are simple in process, which can not only reduce the production cost but also achieve a high yield of mass production. The touch screen as provided in the embodiments of the invention comprises: a transparent substrate; a first patterned transparent eclectically conductive layer; a patterned insulating layer and a second patterned transparent eclectically conductive layer, which are formed above said transparent substrate successively, wherein among said first patterned transparent electrically conductive layer and said second patterned transparent electrically conductive layer, one is formed with a plurality of drive lines, and the other is formed with a plurality of induction lines; the pattern of said insulating layer is identical with that of said first patterned transparent electrically conductive layer, or identical with that of said second patterned transparent electrically conductive layer.

A semiconductor package structure includes an encapsulant, a first chip, a second chip, a first redistribution layer and a second redistribution layer. The encapsulant has a first surface and a second surface opposite to each other. The first chip is in the encapsulant, wherein the first chip includes a plurality of contact pads exposed from the first surface of the encapsulant. The second chip is in the encapsulant, wherein second chip includes a plurality of contact pads exposed from the second surface of the encapsulant. The first redistribution layer is over the first surface of the encapsulant and electrically connected to the contact pads of the first chip. The second redistribution layer is over the second surface of the encapsulant and electrically connected to the contact pads of the second chip.

A circuit board with a heat-recovery function includes a substrate, a heat-storing device, and a thermoelectric device. The heat-storing device is embedded in the substrate and connected to a processor for performing heat exchange with the processor. The thermoelectric device embedded in the substrate includes a first metal-junction surface and a second metal-junction surface. The first metal-junction surface is connected to the heat-storing device for performing heat exchange with the heat-storing device. The second metal-junction surface is joined with the first metal-junction surface, in which the thermoelectric device generates an electric potential by a temperature difference between the first metal-junction surface and the second metal-junction surface.

A printed circuit board includes: a glass layer having a through-hole penetrating between an upper surface and a lower surface thereof; a through-via including a via metal layer disposed on a wall surface of the through-hole and a first insulating material disposed in at least a portion of a space between portions of the via metal layer in the through-hole; a first wiring layer disposed on the upper surface of the glass layer, at least a portion of the first wiring layer connected to an upper side of the through-via; a second wiring layer disposed on the lower surface of the glass layer, at least a portion of the second wiring layer connected to a lower side of the through-via; and a second insulating material covering at least a portion of an external surface of the glass layer. The first and second insulating materials include substantially the same material.

A manufacturing method of an interposed substrate is provided. A photoresist layer is formed on a metal carrier. The photoresist layer has plural of openings exposing a portion of the metal carrier. Plural of metal passivation pads and plural of conductive pillars are formed in the openings. The metal passivation pads cover a portion of the metal carrier exposed by openings. The conductive pillars are respectively stacked on the metal passivation pads. The photoresist layer is removed to expose another portion of the metal carrier. An insulating material layer is formed on the metal cattier. The insulating material layer covers the another portion of the metal carrier and encapsulates the conductive pillars and the metal passivation pads. An upper surface of the insulating material layer and a top surface of each conductive pillar are coplanar. The metal carrier is removed to expose a lower surface of the insulating material layer.

A printed wiring board includes a lowermost resin insulating layer, a first conductor layer formed on a first surface of the lowermost resin insulating layer, a conductor post formed in the lowermost resin insulating layer such that the conductor post has an upper surface facing the first surface and a lower surface on the opposite side with respect to the upper surface, a semiconductor element embedded in the lowermost resin insulating layer such that the semiconductor element has an electrode facing the first surface and is positioned on a second surface side of the lowermost resin insulating layer, and via conductors formed in the lowermost resin insulating layer and including a first via conductor and a second via conductor such that the first via conductor is connecting the first conductor layer and the conductor post and that the second via conductor is connecting the first conductor layer and the electrode.