A method includes the following steps. A seed layer is formed over a structure having at least one semiconductor die. A first patterned photoresist layer is formed over the seed layer, wherein the first patterned photoresist layer includes a first opening exposing a portion of the seed layer. A metallic wiring is formed in the first opening and on the exposed portion of the seed layer. A second patterned photoresist layer is formed on the first patterned photoresist layer and covers the metallic wiring, wherein the second patterned photoresist layer includes a second opening exposing a portion of the metallic wiring. A conductive via is formed in the second opening and on the exposed portion of the metallic wiring. The first patterned photoresist layer and the second patterned photoresist layer are removed. The metallic wiring and the conductive via are laterally wrapped around with an encapsulant.

A printed circuit board includes: a first insulating layer; a first circuit layer disposed on one surface of the first insulating layer; a second insulating layer disposed on the first insulating layer and covering at least a portion of the first circuit layer; a via conductor passing through the second insulating layer and connected to the first circuit layer; a via land connected to the via conductor in an upper portion of the via conductor; and a second circuit layer disposed on the second insulating layer and connected to the via land. The via conductor and the via land have a first interface where the via conductor and the via land are in contact with each other.

A flexible printed circuit board includes a base layer and a pattern line. At least one communication hole penetrating opposite surfaces of the base layer. The pattern line includes two conductive circuit layers formed on the opposite surfaces of the base layer. At least one conductive pole are formed in the at least one communication hole and electrically connects the two conductive circuit layers. A gap being is formed between the conductive pole and the base layer.

A multi-phase busbar for conducting electric energy includes: a base layer of an insulating material; a first conducting layer of a sheet metal; a first insulating layer of an insulating material arranged on the first conducting layer; a second conducting layer of a sheet metal arranged on the insulating layer; and a second layer of an electrically insulating material which is arranged on the second conducting layer. The first and/or second insulating layers include spacers, each spacer including a layer of a rigid insulating material. At least one of the spacers is glued to an electrically insulating coating of the first and/or second conducting layer, and/or at least one of the spacers is glued to an electrically conductive surface of an uncoated first and/or second conducting layer by an adhesive.

Provide are a method for manufacturing a wiring board or a wiring board material, and the wiring board obtained by the method, which allows columnar metal members to be inserted into the wiring board at once using a simple operation, enables alignment without requiring strict accuracy, can handle columnar metal members having different shapes, and imparts sufficiently high adhesive strength to the columnar metal members.

The method includes the steps of: laminating a laminate material LM including the support sheet 10 having the columnar metal members 14 formed thereon, a wiring board WB or a wiring board material WB′ having a plurality of openings in portions corresponding to the columnar metal members 14, and a prepreg 16′ having a plurality of openings in portions corresponding to the columnar metal members 14 and containing a thermosetting resin such that the columnar metal members 14 are positioned in the respective openings; integrating the laminate material LM by heating and pressing to obtain a laminate LB including a thermosetting resin filled between an inner surface of each of the openings of the wiring board WB or the wiring board material WB′ and each of the columnar metal members 14; and peeling at least the support sheet 14 from the laminate LB.

Electronic substrates, contact pads for electronic substrates, and related methods are disclosed. Electronic substrates may include an electrically conductive layer that forms at least one contact pad and at least one metal trace on a non-conductive layer. The contact pads are arranged with greater thicknesses or heights above the non-conductive layer than the metal traces. Dielectric layers are disclosed that cover the metal traces while leaving top surfaces of the contact pads exposed. Top surfaces of the dielectric layers may be arranged to be coplanar with top surfaces of the contact pads to provide electronic substrates having generally planar top faces. Bottom faces of electronic substrates may include mounting pads that are coplanar with additional dielectric layers. Methods are disclosed that include forming dielectric layers to cover contact pads and metal traces, and removing surface portions of the dielectric layers until the contact pads are accessible through the dielectric layers.

An embodiment includes an apparatus comprising: a rod-shaped substrate including a rod long axis; a first layer, including a first interconnect, substantially surrounding the substrate in a first plane that is orthogonal to the rod long axis; and a second layer, including a second interconnect, substantially surrounding the first layer in the first plane. Other embodiments are described herein.

A method for manufacturing a circuit board with embedded conductive circuits includes providing a first circuit substrate having a first support board and a first peelable film, providing a second circuit substrate having a second support board and a second peelable film, providing an insulating layer to obtain an intermediate body, pressing the intermediate body, and removing the first support board, the first peelable film, the second support board, and the second peelable film. The first circuit substrate includes a first circuit layer. The second circuit substrate includes a second circuit layer. The first circuit layer is electrically coupled to the second circuit layer through the insulating layer.

In a wiring base body of a printed wiring board, a conductive post including a wiring portion and a wiring are embedded in an insulating resin film. Therefore, even in a region in which a wiring portion is formed, the wiring base body is not increased in thickness. In addition, even in a region in which a wiring is formed, the wiring base body is not increased in thickness. Therefore, it is possible to obtain a printed wiring board having high flatness by stacking a plurality of wiring base bodies and constituting a printed wiring board.

Electronic substrates, contact pads for electronic substrates, and related methods are disclosed. Electronic substrates may include an electrically conductive layer that forms at least one contact pad and at least one metal trace on a non-conductive layer. The contact pads are arranged with greater thicknesses or heights above the non-conductive layer than the metal traces. Dielectric layers are disclosed that cover the metal traces while leaving top surfaces of the contact pads exposed. Top surfaces of the dielectric layers may be arranged to be coplanar with top surfaces of the contact pads to provide electronic substrates having generally planar top faces. Bottom faces of electronic substrates may include mounting pads that are coplanar with additional dielectric layers. Methods are disclosed that include forming dielectric layers to cover contact pads and metal traces, and removing surface portions of the dielectric layers until the contact pads are accessible through the dielectric layers.