A method for making a via (3) in a carrier layer (1) made of a ceramic comprising:

providing the carrier layer (1),

realizing a passage recess (2) in the carrier layer (1),

at least partially filling the passage recess (2) with a paste (3), and

performing a bonding process, in particular an active soldering process or a DCB process, for bonding a metallization (5) to the carrier layer (1), the via (3′) being realized from the paste (3) in the passage recess (2) when the bonding process is performed.

A method for manufacturing a multilayer coil includes preparing a first substrate by forming a first conductor pattern on a first insulating base material layer, preparing a second substrate by forming a second conductor pattern on a second insulating base material layer, and joining a surface of the first substrate on which the first conductor pattern is formed and a surface of the second substrate on which the second conductor pattern is formed together with only a joining layer made of a thermoplastic resin interposed therebetween. Amounts of deformation of the first and second insulating base material layers are less than that of the joining layer at a fusion temperature. The first and second conductor patterns are each a coil pattern having a coil axis that extends in a lamination direction in which the first substrate and the second substrate are laminated together.

A printed circuit board includes: an insulating layer including a cavity formed therein, the cavity being recessed into the insulating layer from a top surface of the insulating layer; a first circuit layer formed inside the insulating layer such that a portion of the first circuit layer is disposed within the cavity; a second circuit layer disposed above the insulating layer; a first surface-treated layer disposed above the portion of the first circuit layer disposed within the cavity; and a second surface-treated layer disposed above the second circuit layer.

A wiring substrate includes: a base material; a first through-hole and a second through-hole that are formed in the base material; magnetic material that is filled in the first through-hole; a third through-hole that is formed in the magnetic material; a first plating film that covers an inner wall surface of the third through-hole; and a second plating film that covers an inner wall surface of the second through-hole and the first plating film. The first plating film includes a first electroless plating film that is in contact with the inner wall surface of the third through-hole, and a first electrolytic plating film that is laminated on the first electroless plating film.

Provided herein is a roll laminate that can desirably reduce scrapes on a metal foil surface even when a long metal foil is wound into a roll, and that can improve the productivity in use of the unwound roll metal foil. The roll laminate includes a long first metal foil and a long second metal foil that are bonded to each other via an adhesive layer, and are wound around a support. The adhesive layer has a thickness of 1 μm or more in at least a part of the layer, and is provided along the longitudinal direction of the first and the second metal foil in at least both edge portions in the width of an overlapping region of the first and the second metal foil viewed in plan.

A method for manufacturing a component carrier includes covering a dielectric layer structure by a metal foil, forming an electroless metal layer on the metal foil, and forming a multi-stage electroplating structure on the electroless metal layer. A component carrier made by the method is further described.

A resin composition comprising one or more cyanate compounds (A) selected from a group consisting of a naphthol aralkyl-based cyanate compound, a naphthylene ether-based cyanate compound, a xylene resin-based cyanate compound, a trisphenolmethane-based cyanate compound, and an adamantane skeleton-based cyanate compound; a polymaleimide compound (B) represented by general formula (1); and a filler (C).

A resin substrate includes an insulating base material in which conductive particles are mixed with resin, and conductor patterns provided on the principal surfaces of the insulating base material. When a length at a position at which a distance between two conductor patterns that are adjacent to each other without directly electrically connecting to each other on the same principal surface of the insulating base material is smallest is indicated by L1 and a length at a position at which a distance between two conductor patterns that face each other without directly electrically connecting to each other between the different principal surfaces of insulating base materials is smallest is indicated by L2, L1 is larger than or equal to L2 (L1 L2).

A package which comprises a chip carrier made of a first material, a body made of a second material differing from the first material and being arranged on the chip carrier so as to form a cavity, a semiconductor chip arranged at least partially in the cavity, and a laminate encapsulating at least one of at least part of the chip carrier, at least part of the body and at least part of the semiconductor chip.

A wiring board includes electronic components, a multilayer core substrate including insulating layers and conductive layers such that the insulating layers include a central insulating layer in the center position of the core in the thickness direction, a first build-up layer including an insulating layer and a conductive layer such that the insulating layer has resin composition different from that of the insulating layers in the core, and a second build-up layer including an insulating layer and a conductive layer such that the insulating layer has resin composition different from that of the insulating layers in the core. The core has cavities accommodating the electronic components, respectively, and including a first cavity and a second cavity such that the first and second cavities have different lengths in the thickness direction and are penetrating through the central layer at centers of the first and second cavities in the thickness direction.