A process of fabricating an electromagnetic circuit includes providing a first sheet of dielectric material including a top surface having at least one conductive trace and depositing a solder bump on the at least one conductive trace. The process further includes applying a second sheet of dielectric material to the first sheet of dielectric material with bond film sandwiched in between, the second sheet of dielectric material having a through-hole providing access to the solder bump. The process further includes bonding the first and second dielectric materials to one another and removing bond film resin from the solder bump. The process further includes machining the solder bump by the drilling or milling process to achieve a desired amount of solder in the solder bump.

A printed circuit board (PCB) for three-dimensional (3D) packaging that may facilitate packaging multiple electronic components therein is provided. The PCB may include one or more loading pads formed around signal or ground vias to facilitate impedance control and reduce likelihood of signal distortion. The loading pads may be formed on a plane in a body of a dielectric layer configured to form the PCB.

A printed wiring board includes a first conductor layer, a resin insulating layer formed on the first conductor layer, a second conductor layer formed on a surface of the insulating layer, and a via conductor formed in an opening formed in the insulating layer such that the via conductor is connecting the first and second conductor layers. The second conductor layer and via conductor include a seed layer and an electrolytic plating layer formed on the seed layer such that the seed layer has a first portion formed on the surface of the insulating layer, a second portion formed on an inner wall surface of the insulating layer in the opening, and a third portion formed on the first conductor layer exposed from the opening and that the first portion has a thickness that is greater than a thickness of the second portion and a thickness of the third portion.

An electronic-component carrier board includes carrier plates formed in a stack, and insulating layers each disposed between two adjacent ones of the carrier plates. Multiple conductive pins extend through the insulating layers and the carrier plates. Multiple conductive wires equal in length and width are provided. Each conductive wire is connected to one of the conductive pins, covered by one of the insulating layers, disposed between two adjacent ones of the carrier plates, and extends outwardly from the stack of the carrier plates. A wiring method for the electronic-component carrier board is also disclosed.

A method includes preparing a substrate including a display area and a non-display area disposed adjacent to the display area, forming first panel magnetic patterns overlapping the non-display area and extending in a first direction on the substrate, forming first film magnetic patterns extending in the first direction on a film, inputting a first magnetism to the first panel magnetic patterns so that the first panel magnetic patterns have a first magnetic property, inputting a second magnetism to the first film magnetic patterns so that the first film magnetic patterns have a second magnetic property, and aligning the film on the substrate so that the first film magnetic patterns overlap the first panel magnetic patterns in a plan view.

A printed wiring board includes a resin insulating layer, via conductors formed in the resin insulating layer, metal posts formed on the via conductors, respectively, and a solder resist layer formed on the resin insulating layer such that the metal posts have lower portions embedded in the solder resist layer and upper portions exposed from the solder resist layer, respectively. The metal posts are formed such that each of the metal posts has a top portion having a diameter in a range of 0.8 to 0.9 times a diameter of a respective one of the lower portions of the metal posts.

The present disclosure relates to a multilayer ceramic substrate preparation method. The multilayer ceramic substrate preparation method according to the present disclosure includes firing a plurality of ceramic green sheets, to create a plurality of ceramic thin films; forming a via hall in each of the plurality of ceramic thin films; filling the via hall of the plurality of ceramic thin films with conductive paste, and heat treating the via hall filled with the conductive paste, to form a via electrode; printing a pattern on a cross section of each of the plurality of ceramic thin films, and heat treating the printed pattern, to form an inner electrode; applying a bonding agent on the cross section of each of the ceramic thin films excluding an uppermost ceramic thin film of the plurality of ceramic thin films; aligning and laminating each of the plurality of ceramic thin films such that each of the plurality of ceramic thin films is electrically connected through the via electrode and the inner electrode; and firing or heat treating the laminated plurality of ceramic thin films.

Provided is a carrier-attached metal foil with which both exposure for rough circuits and exposure for fine circuits in wiring formation can be performed based on the same alignment marks, and as a result, rough circuits and fine circuits can be simultaneously formed in a one-stage circuit formation process. This carrier-attached metal foil is a carrier-attached metal foil including a carrier, a release layer provided on at least one surface of the carrier, and a metal layer provided on the release layer, wherein the carrier-attached metal foil includes: a wiring region throughout which the carrier, the release layer, and the metal layer are present; and at least two positioning regions provided on the at least one surface of the carrier-attached metal foil and forming alignment marks used for positioning in wiring formation involving exposure and development.

A method includes preparing a substrate including a display area and a non-display area disposed adjacent to the display area, forming first panel magnetic patterns overlapping the non-display area and extending in a first direction on the substrate, forming first film magnetic patterns extending in the first direction on a film, inputting a first magnetism to the first panel magnetic patterns so that the first panel magnetic patterns have a first magnetic property, inputting a second magnetism to the first film magnetic patterns so that the first film magnetic patterns have a second magnetic property, and aligning the film on the substrate so that the first film magnetic patterns overlap the first panel magnetic patterns in a plan view.

A printed circuit board includes a coreless substrate including an insulating body and a plurality of core wiring layers disposed on or within the insulating body, a build-up insulating layer covering at least a portion of each of an upper surface and a lower surface of the coreless substrate, and a build-up wiring layer disposed on at least one of an upper surface and a lower surface of the build-up insulating layer. A through-opening penetrates through the insulating body and is configured to receive an electronic component therein, and the first build-up insulating layer extends into the through-opening to embed the electronic component.