A method includes preparing a substrate including a display area and a non-display area disposed adjacent to the display area, forming first panel magnetic patterns overlapping the non-display area and extending in a first direction on the substrate, forming first film magnetic patterns extending in the first direction on a film, inputting a first magnetism to the first panel magnetic patterns so that the first panel magnetic patterns have a first magnetic property, inputting a second magnetism to the first film magnetic patterns so that the first film magnetic patterns have a second magnetic property, and aligning the film on the substrate so that the first film magnetic patterns overlap the first panel magnetic patterns in a plan view.

A method of making a fusion bonded circuit structure. A substrate is provided with a seed layer of a conductive material. A first resist layer is deposited on the seed layer. The first resist layer is processed to create first recesses corresponding to a desired first circuitry layer. The first recesses expose, portions of the seed layer of conductive material. The substrate is electroplated to create first conductive traces defined by the first recesses. The first resist layer is removed to reveal the first conductive traces. The substrate is etched to remove exposed portions of the seed layer adjacent the first conductive traces. A portion of the seed layer is interposed between the first conductive traces and the substrate. A first layer of LCP is fusion boned to the first major surface of the substrate to encapsulate the first conductive traces in an LCP material. The first LCP layer can be laser drilled to expose the conductive traces.

A printed wiring board includes a first conductor layer, a first insulating layer on the first conductor layer, a second conductor layer on the first insulating layer, a second insulating layer on the second conductor layer, a third conductor layer on the second insulating layer, a first via conductor in the first insulating layer such that the first via conductor is penetrating through the first insulating layer and connecting the first and second conductor layers, a second via conductor in the second insulating layer such that the second via conductor is penetrating through the second insulating layer and connecting the second and third conductor layers, and a magnetic resin portion formed in opening of the first insulating layer and covering part of the first conductor layer such that the second conductor layer is not formed in a region of the first insulating layer where the magnetic resin portion is formed.

A composite article includes a conductive layer on at least a portion of a flexible substrate, wherein the conductive layer has a conductive surface. A patterned layer of a low surface energy material is on a first region of the conductive surface. An overcoat layer free of conductive particulates is on a first portion of a second region of the conductive surface unoccupied by the patterned layer. A via is in a second portion of the second region of the conductive surface between an edge of the patterned layer of the low surface energy material and the overcoat layer. A conductive material is in the via to provide an electrical connection to the conductive surface.

A multilayer bus board comprising a multilayer stacked assembly including a plurality of electrically conductive first layers, and at least one second dielectric layer disposed between adjacent first layers; and a frame formed of a dielectric material, the frame encapsulating at least a portion of the multilayer stacked assembly and mechanically maintaining the first and second layers in secure aligned abutting relation.

A FPCB includes a base layer defining at least one first through hole. A conductive paste block is formed in each first through hole. Each conductive paste block includes a first and a second end portion. The base layer has opposite surfaces, and a first conductive wiring layer is formed on each surface of the base layer. The first end portion at least protrudes from the base layer and is exposed from the first conductive wiring layer. An insulating layer and a second conductive wiring layer are formed on each first conductive wiring layer. At least one second through hole is defined in each insulating layer. The second through hole positioned near the first end portion extends to the first end portion and forms a recess. A conductive via is formed in each second through hole and the corresponding recess, and is electrically connected to the conductive paste block.

A multilayer wiring board having a high degree of freedom of wiring design and realizing high-density wiring, and a method to simply manufacture the multilayer wiring board is provided. A core substrate with two or more wiring layers provided thereon through an electrical insulating layer. The core substrate has a plurality of throughholes filled with an electroconductive material, and the front side and back side of the core substrate have been electrically connected to each other by the electroconductive material. The throughholes have an opening diameter in the range of 10 to 100 m. An insulation layer and an electroconductive material diffusion barrier layer are also provided, and the electroconductive material is filled into the throughholes through the insulation layer. A first wiring layer provided through an electrical insulating layer on the core substrate is connected to the electroconductive material filled into the throughhole through via.

A multilayer ceramic substrate includes: a plurality of ceramic layers 300a, 300b stacked together; a via hole 400a, 400b provided in each of the plurality of ceramic layers, the via holes of the plurality of ceramic layers being connected together in a layer stacking direction of the plurality of ceramic layers; a via wire 406a, 406b including an electrical conductor filled into each of the via holes; a first conductor 404a, 404b provided on an upper surface of at least one of the plurality of ceramic layers, the first conductor having an annular or partially annular shape surrounding the via wire; and a second conductor 403a, 403b including a first portion and a second portion, the first portion being located outside the first conductor on the upper surface of the at least one ceramic layer, the second portion overlying the first conductor, and an inner rim of the second portion being located outside an inner rim of the first conductor, wherein a thickness of the first conductor 404a, 404b is greater than a thickness of the second conductor 403a, 403b.

A method of estimating a virtual contour of an insulating material is disclosed. The method includes the following steps: obtaining a first and a second images at a pair of diagonal locations of the insulating material respectively; determining a first and a second corner locations from the first and the second images respectively; selecting a first set of longitudinal end-point positions and a first set of transverse end-point positions within a range between a first specific distance and a second specific distance from the first corner location; selecting a second set of longitudinal end-point positions and a second set of transverse end-point positions within a range between the first specific distance and the second specific distance from the second corner location; and determining a first transverse axis direction, a first longitudinal axis direction, a second transverse axis direction and a second longitudinal axis direction based on these positions.

A sheet-fed system designed to print multilayer PCBs is introduced. The system consists of four main blocks; a drilling station, a patterning station, a stacking/bonding station, and a sintering zone. The substrate PCB is shuttled between these various stations, to have vias drilled, to be attached to stacks of previously-processed layers, to be covered with conductive paths by means of the aforementioned ink, and to have the ink sintered under a controlled temperature and atmosphere. Patterning is accomplished by means of a novel two-step method involving both high-temperature conductive elements, low-temperature conductive elements, and flux. Two such compositions are successively applied and individually sintered to form a single conductive path; the second application serves to fill the porosities of the first layer. By this method, a highly-conductive trace is obtained without requiring high temperatures, which in turn allows use of common substrates including polymers.