There are provided a package board, a method for manufacturing the same, and a package on package having the same. The package board according to an exemplary embodiment of the present disclosure includes a first insulating layer formed with a cavity having a penetrating shape; and a first connection pad formed to penetrate through the first insulating layer and formed at one side of the cavity.

A wiring board includes a base substrate, a semiconductor element embedded in the substrate and having active and non-active surfaces such that the semiconductor has a terminal on the active surface, a first build-up layer including an insulating layer and first conductor pads such that the first conductor pads have exposed surfaces exposed from a surface of the insulating layer on the opposite side with respect to the substrate, and a second build-up layer including an insulating layer and second conductor pads such that the second conductor pads have exposed surfaces exposed from a surface of the insulating layer on the opposite side with respect to the substrate. The insulating layer in the first build-up includes resin material and reinforcing material, the insulating layer in the second build-up includes resin material and reinforcing material, and the first conductor pads is embedded in the insulating layer in the first build-up.

An arrangement, a method of manufacturing component carriers and a component carrier are provided. The arrangement includes a central carrier structure having a front side and a back side, a first layer stack having a first surface structure made of another material than the interior of the first layer stack and covered by a first release layer which is attached to the front side, and a second layer stack covered by a second release layer which is attached to the back side.

A wiring structure includes a conductive structure and at least one conductive through via. The conductive structure includes a plurality of dielectric layers, a plurality of circuit layers in contact with the dielectric layers, and a plurality of dam portions in contact with the dielectric layers. The dam portions are stacked on and contact one another. The conductive through via extends through the dam portions.

A non-planar printed circuit board has an interior surface and an exterior surface. Between the interior surface and exterior surfaces are layers of conductive and dielectric materials. Passive and active electrical components are embedded within the interior and exterior surfaces. A hollow region is defined by the interior surface of the non-planar circuit board. The non-planar printed circuit board is manufactured on a mandrel having a non-planar shape such as, for example, a cylinder or sphere so as to form a hollow, curved non-planar structure.

A manufacturing method of a metal structure is disclosed, which includes the following steps: forming a seed layer on a substrate; forming a patterned metal layer on the seed layer, wherein the patterned metal layer includes a metal member; forming a first patterned photoresist layer on the seed layer, wherein a thickness of the first patterned photoresist layer is less than a thickness of the patterned metal layer; and performing a first patterning process to the seed layer through the first patterned photoresist layer to form a patterned seed layer, wherein after the first patterning process, the metal member includes a first part and a second part, the first part is disposed between the patterned seed layer and the second part, and a width of the first part is greater than a width of the second part.

A method of fabricating an interposer includes: providing a carrier substrate; forming a unit redistribution layer on the carrier substrate, the unit redistribution layer including a conductive via plug and a conductive redistribution line; and removing the carrier substrate from the unit redistribution layer. The formation of the unit redistribution layer includes: forming a first photosensitive pattern layer including a first via hole pattern; forming a second photosensitive pattern layer including a second via hole pattern and a redistribution pattern on the first photosensitive pattern layer; at least partially filling insides of the first via hole pattern, the second via hole pattern, and the redistribution pattern with a conductive material; and performing planarization to make a top surface of the unit redistribution layer flat. According to the method, no undercut occurs under a conductive structure and there are no bubbles between adjacent conductive structures, thus device reliability is enhanced and pattern accuracy is realized.

A method for producing a package substrate for mounting a semiconductor device includes:

forming a first substrate by forming a laminate in which a first metal layer that has a thickness of 1 μm to 70 μm and that is peelable from a core resin layer, a first insulating resin layer, and a second metal layer are arranged on both sides of the core resin layer having a thickness of 1 μm to 80 μm, and heating and pressurizing the laminate simultaneously;

forming a pattern on the second metal layer;

forming a second substrate by heating and pressurizing a laminate formed by arranging a second insulating resin layer and a third metal layer on a surface of the second metal layer; and

peeling, from the core resin layer, a third substrate including the first metal and insulating resin layers, the second metal and insulating layers, and the third metal layer.

Resin sheets which includes a support and a resin composition layer in contact on the support, and which are characterized in that an extracted water conductivity A of a cured product of the resin composition layer when extracted at 120° C. for 20 hours is 50 μS/cm or less and an extracted water conductivity B of the cured product of the resin composition layer when extracted at 160° C. for 20 hours is 200 μS/cm or less, can provide a thin insulating layer having excellent insulating properties.

Embodiments of the present invention describe a semiconductor package having an embedded die. The semiconductor package comprises a coreless substrate that contains the embedded die. The semiconductor package provides die stacking or package stacking capabilities. Furthermore, embodiments of the present invention describe a method of fabricating the semiconductor package that minimizes assembly costs.