According to one aspect, a glass-free pre-impregnated material includes a polybenzimidazole (PBI) sheet and a partially cured resin encapsulating the PBI sheet. According to another aspect, a process of forming a glass-free pre-impregnated material includes encapsulating a PBI sheet within a resin and partially curing the resin to form the glass-free pre-impregnated material. According to yet another aspect, a printed circuit board comprises a glass-free dielectric layer that includes a PBI sheet encapsulated within a cured resin.

A manufacturing method of a carrier structure includes: A build-up circuit layer is formed on a carrier. The build-up circuit layer includes at least one first circuit layer, at least one first dielectric layer, a second circuit layer, a second dielectric layer, and a plurality of conductive vias. The first circuit layer is located on the carrier and includes at least one first pad, which is disposed relative to at least one through hole of the carrier. The first dielectric layer is located on the first circuit layer. The second circuit layer is located on the first dielectric layer and includes at least one second pad. The second dielectric layer is located on the second circuit layer and includes at least one opening exposing the second pad. The conductive via penetrates the first dielectric layer and is electrically connected to the first circuit layer and the second circuit layer.

An adapter board is described having a substrate having a width, a length and a depth and at least one electrical component placed one of within the substrate and on a surface of the substrate. The adapter board may also have a first pad positioned on the substrate, the first pad connected to the at least one electrical component through a first via. The adapter board may also have a second pad positioned on the substrate, the second pad connected to the at least one electrical component through a second via, wherein at least a portion of the adapter board is configured through an additive manufacturing process and wherein the substrate is configured to be installed within a downhole tool.

A flexible display device that can suppress spread of cracks of an inorganic layer is provided. A flexible display device includes a flexible substrate including a display area and a periphery surrounding the display area, an inorganic layer formed on the flexible substrate, a display unit formed on the display area, and a thin film encapsulation layer covering the display unit. The inorganic layer includes an opening disposed on a periphery between edges of the flexible substrate and the thin film encapsulation layer.

A camera module of an embodiment may comprise: a first holder in which a filter is mounted; a lens barrel that is provided to be vertically movable in a first direction with respect to the first holder; a lens operating device that comprises a terminal and moves the lens barrel in the first direction; a first circuit board that is disposed under the first holder and on which an image sensor is mounted; a soldering portion for electrically connecting the terminal of the lens operating device to the first circuit board; and a coupling reinforcement portion that is disposed to face the soldering portion and couples the lens operating device and the first circuit board.

A method of manufacturing a constituent for a component carrier is disclosed. The method includes providing an electrically conductive structure, forming a highly thermally conductive and electrically insulating or semiconductive structure on the electrically conductive structure, and subsequently, attaching a thermally conductive and electrically insulating structure, having a lower thermal conductivity than the highly thermally conductive and electrically insulating or semiconductive structure, on an exposed surface of the highly thermally conductive and electrically insulating or semiconductive structure.

A ceramic copper circuit board according to an embodiment includes a ceramic substrate and a first copper part. The first copper part is bonded at a first surface of the ceramic substrate via a first brazing material part. The thickness of the first copper part is 0.6 mm or more. The side surface of the first copper part includes a first sloped portion. The width of the first sloped portion is not more than 0.5 times the thickness of the first copper part. The first brazing material part includes a first jutting portion jutting from the end portion of the first sloped portion. The length of the first jutting portion is not less than 0 m and not more than 200 m. The contact angle between the first jutting portion and the first sloped portion is 65 or less.

A system includes a stress-engineered substrate comprising at least one tensile stress layer having a residual tensile stress and at least one compressive stress layer having a residual compressive stress. The at least one tensile layer and the at least one compressive layer are coupled such that the at least one tensile stress layer and the at least one compressive stress layer are self-equilibrating. At least one functional device is disposed on the stress-engineered substrate. The stress-engineered substrate is configured to fracture in response to energy applied to the substrate. Fracturing the stress-engineered substrate also fractures the functional device. The system includes at least one decoy device. Fragments of the decoy device are configured to obscure one or more physical characteristics of the functional device and/or one or more functional characteristics of the functional device after the functional device is fractured.

A carrier structure includes a carrier having at least one through hole penetrating the carrier and a build-up circuit layer located on the carrier and including at least one first circuit layer, at least one first dielectric layer, a second circuit layer, a second dielectric layer, and a plurality of conductive vias. The first circuit layer is located on a first surface of the carrier and includes at least one first pad disposed relative to the through hole. The first dielectric layer is located on the first circuit layer. The second circuit layer is located on the first dielectric layer and includes at least one second pad. The second dielectric layer is located on the second circuit layer and includes at least one opening exposing the second pad. The conductive vias penetrate the first dielectric layer and are electrically connected to the first and second circuit layers.

A circuit board includes an insulating layer; a capacitor which is provided in the insulating layer and includes a dielectric layer, a first conductor layer provided on a first surface of the dielectric layer and including a first opening part, and a second conductor layer provided on a second surface opposite to the first surface of the dielectric layer and including a second opening part at a position corresponding to the first opening part; a first conductor via provided in the insulating layer, penetrating the dielectric layer, the first opening part and the second opening part, and being smaller than the first opening part and the second opening part in plan view; a second conductor via provided in the insulating layer and making contact with the second conductor layer; and a third conductor layer provided on the insulating layer and electrically coupled to the first and the second conductor vias.