A combination underfill-dam and electrical-interconnect structure for an opto-electronic engine. The structure includes a first plurality of electrical-interconnect solder bodies. The first plurality of electrical-interconnect solder bodies includes a plurality of electrical interconnects. The first plurality of electrical-interconnect solder bodies, is disposed to inhibit intrusion of underfill material into an optical pathway of an opto-electronic component for the opto-electronic engine. A system and an opto-electronic engine that include the combination underfill-dam and electrical interconnect structure are also provided.

A method includes forming one or more trenches in a first substrate, forming one or more vias in a second substrate, aligning at least a first trench in the first substrate with at least a first via in the second substrate, and sealing the first substrate to the second substrate by filling the first via and the first trench with solder material using injection molded soldering.

A method includes forming one or more vias in a substrate, forming a first photoresist layer on a top surface of the substrate and a second photoresist layer on a bottom surface of the substrate, patterning the first photoresist layer and the second photoresist layer to remove at least a first portion of the first photoresist layer and at least a second portion of the second photoresist layer, filling the one or more vias, the first portion and the second portion with solder material using injection molded soldering, and removing remaining portions of the first photoresist layer and the second photoresist layer.

A method includes forming one or more trenches in a first substrate, forming one or more vias in a second substrate, aligning at least a first trench in the first substrate with at least a first via in the second substrate, and sealing the first substrate to the second substrate by filling the first via and the first trench with solder material using injection molded soldering.

A method includes forming one or more vias in a substrate, forming at least one liner on at least one sidewall of at least one of the vias, and filling said at least one via with solder material using injection molded soldering. The at least one liner may comprise a solder adhesion layer, a barrier layer, or a combination of a barrier layer and a solder adhesion layer.

Techniques and mechanisms for controlling configurable circuitry including an antifuse. In an embodiment, the antifuse is disposed in or on a substrate, the antifuse configured to form a solder joint to facilitate interconnection of circuit components. Control circuitry to operate with the antifuse is disposed in, or at a side of, the same substrate. The antifuse is activated based on a voltage provided at an input node, where the control circuitry automatically transitions through a pre-determined sequence of states in response to the voltage. The pre-determined sequence of states coordinates activation of one or more fuses and switched coupling one or more circuit components to the antifuse. In another embodiment, multiple antifuses, variously disposed in or on the substrate, are configured each to be activated based on the voltage provided at an input node.

A method includes forming one or more vias in a first layer, forming one or more vias in at least a second layer different than the first layer, aligning at least a first via in the first layer with at least a second via in the second layer, and bonding the first layer to the second layer by filling the first via and the second via with solder material using injection molded soldering.

A position indicator includes: a chassis; a substrate disposed inside the chassis; a coil; capacitors disposed on the substrate; interconnects disposed on the substrate such that each at least partially connects a respective one of the capacitors to the coil in parallel; and pairs of land patterns. Each pair of land patterns includes a first land pattern and a second land pattern. Each of the interconnects has a first end connected to a first end of the coil and a second end connected to a second end of the coil, and is connected to one of the capacitors. The pairs of land patterns are disposed such that each of the interconnects is at least partially interposed between the first land pattern and the second land pattern of one of the pairs of land patterns.

A stress reduction interposer is provided for disposition between first and second solder materials of first and second electronic devices, respectively. The stress reduction interposer includes a plate element having a central portion and a periphery surrounding the central portion and being formed to define first cavities having an upper area limit at the periphery and a second cavity having a lower area limit, which is higher than the upper area limit, at the central portion and third and fourth solder materials being disposable in the second cavity and in the first cavities, respectively, to be electrically communicative with the first and second solder materials. The third solder material is more compliant and has a higher melting temperature than at least the second and fourth solder materials.

A stress reduction interposer is provided for disposition between first and second solder materials of first and second electronic devices, respectively. The stress reduction interposer includes a plate element having a central portion and a periphery surrounding the central portion and being formed to define first cavities having an upper area limit at the periphery and a second cavity having a lower area limit, which is higher than the upper area limit, at the central portion and third and fourth solder materials being disposable in the second cavity and in the first cavities, respectively, to be electrically communicative with the first and second solder materials. The third solder material is more compliant and has a higher melting temperature than at least the second and fourth solder materials.