A component carrier includes (a) a base structure having a surface with a surface profile; (b) a first dielectric layer formed on the surface of the base structure and (c) a second dielectric layer formed on the first dielectric layer. The first dielectric layer has a first main surface with a first surface profile. The first main surface faces away from the surface of the base structure. The first surface profile corresponds to the surface profile of the base structure. The second dielectric layer includes a second main surface with a second surface profile. The second main surface faces away from the surface of the base structure. The second surface profile differs from the surface profile of the base structure. A manufacturing method uses an auxiliary sheet for pressing the first dielectric layer on the main surface. The auxiliary sheet is removed before pressing the second dielectric layer.

A package includes a conductive pad, with a plurality of openings penetrating through the conductive pad. A dielectric layer encircles the conductive pad. The dielectric layer has portions filling the plurality of openings. An Under-Bump Metallurgy (UBM) includes a via portion extending into the dielectric layer to contact the conductive pad. A solder region is overlying and contacting the UBM. An integrated passive device is bonded to the UBM through the solder region.

A ceramic circuit substrate having high bonding performance and excellent thermal cycling resistance properties, having a circuit pattern provided on a ceramic substrate with a braze material layer interposed therebetween, and a protruding portion formed by the braze material layer protruding from the outer edge of the circuit pattern, wherein: the braze material layer includes Ag, Cu, Ti, and Sn or In; and an Ag-rich phase is formed continuously for 300 μm or more, towards the inside, from an outer edge of the protruding portion, along a bonding interface between the ceramic substrate and the circuit pattern, and has a bonding void ratio of 1.0% or less.

This heat sink integrated insulating circuit substrate includes: a heat sink including a top plate part and a cooling fin; an insulating resin layer formed on the top plate part of the heat sink; and a circuit layer made of metal pieces arranged on a surface of the insulating resin layer opposite to the heat sink, wherein, when a maximum length of the top plate part is defined as L, an amount of warpage of the top plate part is defined as Z, and deformation of protruding toward a bonding surface side of the top plate part of the heat sink is defined as a positive amount of warpage, and a curvature of the heat sink is defined as C=|(8×Z)/L.sup.2|, a ratio P/C.sub.max between a maximum curvature C.sub.max(l/m) of the heat sink during heating from 25° C. to 300° C. and peel strength P (N/cm) of the insulating resin layer satisfies P/C.sub.max>60.

This application provides a stiffener ring and a surface packaging assembly. The stiffener ring is configured to correct warpage of a substrate of the surface packaging assembly. The stiffener ring includes an annular stiffener ring body and an adjustment block that is disposed at a same layer as the stiffener ring body and that is fastened to at least one corner of the stiffener ring body.

A coefficient of thermal expansion of the adjustment block is less than a coefficient of thermal expansion of the stiffener ring body. Coordination between the adjustment block and the stiffener ring body alleviates an “M-shape” overpressure phenomenon of a warpage deformation caused by the stiffener ring to the substrate at a high temperature, reduces warpage of the substrate, and improves flatness of the surface packaging assembly.

A circuit board according to an embodiment includes an insulating layer; a circuit pattern disposed on an upper surface of the insulating layer; a first solder resist disposed on an upper surface of the insulating layer and having a height smaller than a height of the circuit pattern; and a second solder resist disposed on an upper surface of the first solder resist and including a first portion having an upper surface lower than an upper surface of the circuit pattern and a second. portion having an upper surface higher than the upper surface of the circuit pattern, wherein the circuit pattern includes: a plurality of first circuit patterns disposed on an upper surface of a first region of the insulating layer, and a plurality of second circuit patterns disposed on an upper surface of a second region of the insulating layer; wherein the first portion of the second solder resist is disposed between the plurality of first circuit patterns to have an upper surface lower than an upper surface of the first circuit pattern; and wherein the second portion of the second solder resist has an upper surface higher than an upper surface of the second circuit pattern, and is disposed to cover the plurality of second circuit patterns between the plurality of second circuit patterns.

A package includes a conductive pad, with a plurality of openings penetrating through the conductive pad. A dielectric layer encircles the conductive pad. The dielectric layer has portions filling the plurality of openings. An Under-Bump Metallurgy (UBM) includes a via portion extending into the dielectric layer to contact the conductive pad. A solder region is overlying and contacting the UBM. An integrated passive device is bonded to the UBM through the solder region.

A ball-grid-array component of a ball-grid array assembly is analyzed prior to reflow. A predicted warping pattern of the ball-grid-array component that is likely to occur during reflow is predicted based on the analyzing. A solder ball ball-grid-array defect that could be caused by the predicted warping pattern is predicted. An initial via suction pattern to mitigate the ball-grid-array defect is assigned. A vacuum head is applied to a via in the ball-grid-array assembly. The solder ball is located at the opposite end of the via from the vacuum head. Suction is applied to the via based on the via suction pattern. The suction draws a portion of the solder ball into the via during reflow.

A semiconductor device includes a semiconductor element, a circuit board, metal wires, and an expanding member. The circuit board has an upper surface and a lower surface opposite the upper surface. The metal wires arc formed on at least one of the upper surface and the lower surface. At least two connection terminals are formed in a terminal formation surface of the semiconductor element which is disposed so as to face the upper surface of the circuit board. The expanding member is fixed to the terminal formation surface of the semiconductor element, has a larger coefficient of linear thermal expansion than the semiconductor element, and has a size larger than the interval between adjacent two of the at least two connection terminals.

A chip-on-film (COF) package includes a film, a driver integrated circuit (IC) chip disposed on the film, an electrode pad disposed on an edge of the film, and a first deformation-preventing member disposed on the film, between the driver IC chip and the electrode pad.