A component carrier includes a stack having at least one electrically conductive layer structure, a first electrically insulating layer structure and a second electrically insulating layer structure. The first electrically insulating layer structure is made of a material which has first physical properties. The second electrically insulating layer structure is made of another material which has second physical properties differing from the first physical properties. The first electrically insulating layer structure and the second electrically insulating layer structure are at least partially in direct physical contact with each other. A method of manufacturing a component carrier is also disclosed.

A method includes attaching a substrate to a carrier, aligning external connectors on a first surface of a first semiconductor package to first conductive pads on a first surface of the substrate facing away from the carrier, and performing a reflow process, where a difference in coefficients of thermal expansion (CTEs) between the substrate and the carrier causes a first shape for the first surface of the substrate during the reflow process, where differences among CTEs of materials of the first semiconductor package causes a second shape for the first surface of the first semiconductor package during the reflow process, and wherein the first shape substantially matches the second shape. The method further includes removing the carrier from the substrate after the reflow process.

An apparatus is described. The apparatus includes a ball grid array (BGA) chip package cooling assembly includes a back plate and a bolster plate. The bolster plate has frame arms. The BGA chip package is to be placed in a window formed by the frame arms and soldered to a region of a printed circuit board. The frame arms surround the region. The printed circuit board is to be subjected to a compressive force between the back plate and the bolster plate.

A system includes a top printed circuit (PCB) including an array of contact pads, a bottom PCB including an array of contact pads, at least one interposer positioned between the top and bottom PCBs, including: an array of top connectors configured to contact the array of contact pads of the top PCB; an array of bottom connectors configured to contact the array of contact pads of the bottom PCB; and interconnections configured to electrically connect the top connectors and the bottom connectors, at least one spacer element positioned between the top PCB and the bottom PCB and configured to contribute to maintaining a specified distance between the top PCB and the bottom PCB; and at least one fastener of the top PCB and the bottom PCB. The system further includes fasteners configured to press the top PCB, the interposer, the bottom PCB, and the spacer layer together.

The disclosure provides a circuit board structure including at least two sub-circuit boards and at least one connector. Each of the sub-circuit boards includes a plurality of carrier units. The connector is connected between the sub-circuit boards, and a plurality of stress-relaxation gaps are defined between the sub-circuit boards.

A multilayer resin substrate includes insulating resin base material layers, and conductor patterns on at least one of the insulating resin base material layers. The conductor patterns include a ground conductor on a main surface of the insulating resin base material layers and extend into a frame shape or a planar shape, and the ground conductor includes openings. An aperture ratio of the openings in an outer peripheral portion of the ground conductor is less than an aperture ratio of the openings in an inner peripheral portion of the ground conductor.

A method for producing a circuit board arrangement includes: providing a first circuit board substrate, providing a second circuit board substrate, arranged substantially planar-parallel to the first circuit board substrate, the first circuit board substrate having an underside and the second circuit board substrate having an upper face, the upper face and the underside being arranged opposite one another, providing first terminal contacts, applied to the underside of the first circuit board substrate, providing second terminal contacts, applied to the upper face of the second circuit board substrate, applying solder paste cylinders to the first terminal contacts, the solder paste cylinders applied to the first terminal contacts by a solder-paste application process with solder paste, the applied solder paste cylinders having in each case a solder-paste-cylinder upper face, and arranging the second terminal contacts of the second circuit board substrate on the solder-paste-cylinder upper faces of the solder paste cylinders.

A component carrier includes a stack having a first electrically insulating layer structure and a first electrically conductive layer structure arranged on the first electrically insulating layer structure. The first electrically insulating layer structure has at least one first covered portion, which is covered by the first electrically conductive layer structure, and at least one first non-covered portion, which is not covered by the first electrically conductive layer structure. The first electrically insulating layer structure defines a recess at the at least one first non-covered portion.

Provided is a method for compensating a stress-sensitive parameter, and the method is applied to an electronic devices. The method includes: calculating (51) a deformation value of a first panel according to a pressure borne by the first panel; calculating (52) according to the deformation value of the first panel a deformation value of a second panel that is deformed due to the deformation of the first panel; calculating (53) according to the deformation value of the second panel a change in a stress-sensitive parameter of a stress-sensitive element on the second panel; and compensating (54) the stress-sensitive parameter according to the change in the stress-sensitive parameter. The quality of the parameters of corresponding electronic elements and electronic modules are thereby improved, ultimately enhancing the performance of electronic device.

Voids are introduced in a copper shape to reduce warpage experienced by a printed circuit board during a reflow process. Copper shapes on an outer layer of a printed circuit board may be used to connect large packages that include ball grid arrays to the printed circuit board. The copper shapes may induce warpage in the printed circuit board during the reflow process. Routing a mesh pattern of voids in the copper shapes may reduce solder ball joint cracking and pad cratering during reflow and make solder joints more reliable. The voids may make the copper shapes less ridged and change the copper heat dissipation profile to remove sharp warpage forces that cause solder joints to experience pad cratering. The voids may be 8 mil×8 mil cuts or indentations in the copper shape.