According to one embodiment, a semiconductor memory system includes a substrate, a plurality of elements and an adhesive portion. The substrate has a multilayer structure in which wiring patterns are formed, and has a substantially rectangle shape in a planar view. The elements are provided and arranged along the long-side direction of a surface layer side of the substrate. The adhesive portion is filled in a gap between the elements and in a gap between the elements and the substrate, where surfaces of the elements are exposed.

A component carrier includes a core having a recess, an electronic component arranged in the recess, a laminated electrically insulating sheet covering at least part of the core and of the electronic component and filling a gap between a lateral surface of the electronic component and a lateral surface of the core in the recess, and a further electrically insulating layer structure laminated on top of the sheet.

Provided is an electronic device including a display panel including a base substrate, pixels, a first insulation layer, and panel pads spaced along a first direction from pixels and each arranged along a second direction crossing the first direction, a circuit board disposed on the display panel and connected to panel pads, and an adhesive interconnect layer disposed between the display panel and the circuit board and electrically connecting the display panel and the circuit board. The circuit board includes a flexible substrate including a top surface facing the base substrate, output pads disposed on the flexible substrate and connected to panel pads, each obliquely extending in the first and second directions and arranged along the second direction, an alignment pad spaced along the second direction from output pads, and a stress relaxation pad disposed between output pads and alignment pads and electrically connected from panel pads.

According to one embodiment, a semiconductor memory system includes a substrate, a plurality of elements and an adhesive portion. The substrate has a multilayer structure in which wiring patterns are formed, and has a substantially rectangle shape in a planar view. The elements are provided and arranged along the long-side direction of a surface layer side of the substrate. The adhesive portion is filled in a gap between the elements and in a gap between the elements and the substrate, where surfaces of the elements are exposed.

A polyphenylene ether resin composition includes a modified polyphenylene ether copolymer, a high-molecular-weight compound, and a crosslinking agent for the modified polyphenylene ether copolymer. The modified polyphenylene ether copolymer includes a substituent having a carbon-carbon unsaturated double bond at a molecular chain end of the modified polyphenylene ether copolymer. The high-molecular-weight compound has a glass transition temperature (Tg) measured by differential scanning calorimetry of 20° C. or lower and has a number-average molecular weight Mn ranging from 1000 to 10000, inclusive. The crosslinking agent includes at least two carbon-carbon unsaturated double bonds per molecule, and includes at least one of dicyclopentadiene acrylate and dicyclopentadiene methacrylate. In a cured state of the polyphenylene ether resin composition, the modified polyphenylene ether copolymer is phase separated from the high-molecular-weight compound.

A ceramic circuit board includes a ceramic substrate and metal layers provided to both surfaces of the ceramic substrate and containing Al and/or Cu, wherein a measurement value α1 of a linear thermal expansion coefficient at 25° C. to 150° C. is 5×10.sup.−6 to 9×10.sup.−6/K, a ratio α1/α2 of the α1 to a theoretical value α2 of the linear thermal expansion coefficient at 25° C. to 150° C. is 0.7 to 0.95, and at least one of the metal layers forms a metal circuit.

An electronic package having a base structure; a layer stack formed over the base structure; and a component embedded at least partially within the base structure and/or within the layer stack. The layer stack has a decoupling layer structure, the decoupling layer structure with a decoupling material having a Young Modulus being smaller than 1 GPa.

Generally, the present disclosure provides example embodiments relating to a package attached to a printed circuit board (PCB). In an embodiment, a structure includes a PCB. The PCB has ball pads arranged in a matrix. Outer ball pads are along one or more outer edges of the matrix, and each of the outer ball pads has a first solder-attach area. Inner ball pads are interior to the matrix, and each of the inner ball pads has a second solder-attach area. The first solder-attach area is larger than the second solder-attach area.

A package includes a conductive pad, with a plurality of openings penetrating through the conductive pad. A dielectric layer encircles the conductive pad. The dielectric layer has portions filling the plurality of openings. An Under-Bump Metallurgy (UBM) includes a via portion extending into the dielectric layer to contact the conductive pad. A solder region is overlying and contacting the UBM. An integrated passive device is bonded to the UBM through the solder region.

A component carrier with a stack having at least one electrically conductive layer structure and a plurality of electrically insulating layer structures and a component embedded in the stack. The plurality of electrically insulating layer structures include a first dielectric structure and a second dielectric structure differing concerning at least one physical property.