Provided is an embedded printed circuit board, including: a first insulating substrate including a first cavity and a second cavity; a first element disposed in the first cavity; an adhesive layer for adhering the first insulating substrate to the first element and including an opening to which the first element is exposed; and an second insulating substrate forming a bonding layer of a lower surface of the first insulating substrate and a bottom surface of the second cavity.

There are provided an electronic device mounting substrate and an electronic apparatus which are capable of miniaturization. An electronic device mounting substrate includes: an insulating base including a frame section; an electrode pad disposed on an upper surface of the frame section; and a first conductor disposed on a side surface of the frame section, the first conductor being electrically connected to the electrode pad, the electrode pad extending over a side surface of the first conductor from the upper surface of the frame section. By suppressing separation of the first conductor from the insulating base by means of the electrode pad, disconnection at the first conductor can be suppressed.

In a high frequency signal line, a first signal line extends along a first dielectric element assembly, a first reference ground conductor extends along the first signal line, a second signal line is provided in or on the second dielectric element assembly and extends along the second dielectric element assembly, a second reference ground conductor is provided in or on the second dielectric element assembly and extends along the second signal line. A portion of a bottom surface at an end of the first dielectric element assembly and a portion of the top surface at an end of the second dielectric element assembly are joined together such that a joint portion of the first and second dielectric element assemblies includes a corner. The second signal line and the first signal line are electrically coupled together. The first and second reference ground conductors are electrically coupled together.

A semiconductor structure includes an insulating layer, a plurality of stepped conductive vias and a patterned circuit layer. The insulating layer includes a top surface and a bottom surface opposite to the top surface. The stepped conductive vias are disposed at the insulating layer to electrically connect the top surface and the bottom surface. Each of the stepped conductive vias includes a head portion and a neck portion connected to the head portion. The head portion is disposed on the top surface, and an upper surface of the head portion is coplanar with the top surface. A minimum diameter of the head portion is greater than a maximum diameter of the neck portion. The patterned circuit layer is disposed on the top surface and electrically connected to the stepped conductive vias.

Devices and methods related to metallization of ceramic substrates for shielding applications. In some embodiments, a ceramic assembly includes a plurality of layers, the assembly including a boundary between a first region and a second region, the assembly further including a selected layer having a plurality of conductive features along the boundary, each conductive feature extending into the first region and the second region such that when the first region and the second region are separated to form their respective side walls, each side wall includes exposed portions of the conductive features capable of forming electrical connection with a conductive shielding layer.

A printed circuit board for mounting electrical components thereupon include: a first side; a second side opposite the first side; electrical connection points disposed on the surface of an exterior edge of the printed circuit board; and wherein the exterior edge of the printed circuit board is between the first side and the second side. Further a method of manufacturing a printed circuit board for mounting electrical components thereupon includes the steps of disposing interconnect structures within the printed circuit board adjacent to at least one edge of the printed circuit board; and removing material from the printed circuit board edge to expose the interconnect structures such that the exposed interconnect structures correspond to a component connection footprint.

System for enabling circuit board surface-slot-edge connections. A main board includes a slot through its surfaces. At least one edge of the slot includes electrical contacts to the main board. An auxiliary board includes a connector component mounted on a surface that opposes a surface of the main board. When the connector component is aligned with the slot, the connector component can protrude vertically through the slot, in addition to moving laterally towards an edge of the slot. Electrical contacts on the edge of the slot can engage with electrical contacts in the connector component. This enables two boards to be arranged closely, without extending the main surface in an orthogonal or lateral direction, using a secure connection provided by a connector attached to the auxiliary board, rather than the main board.

An electrical connector includes a housing having a cavity and a wafer stack received in the cavity. The wafer stack includes a plurality of electrical wafers arranged parallel to each other within the cavity. Each wafer includes a dielectric body and a leadframe having plural conductors held in the dielectric body, the conductors having terminating contacts and mating contacts with leads therebetween. The terminating contacts are both horizontally staged and vertically staged and exposed in a pocket of the dielectric body for electrical termination. The mating contacts being exposed for electrical connection. The electrical connector includes a flex harness includes a plurality of FPCBs. The FPCBs are electrically connected to corresponding wafers. Each FPCB has a stepped mating interface with conductors along the stepped mating interface configured to be electrically connected to corresponding terminating contacts.

A printed circuit board (PCB) includes a stack of core layers disposed one over another, and electrically conductive interconnects extending vertically in the stack. Each of the core layers includes a substrate having opposite major surfaces, an electrically conductive active trace extending along at least one of the major surfaces, and an indicium. The stack also has an exposed edge where the indicia of the layers are together revealed. The indicia provide identifying and/or fiducial information about the PCB.

A system for transmitting or receiving signals may include a dielectric substrate having a major face, a communication circuit, and an electromagnetic-energy directing assembly. The circuit may include a transducer configured to convert between RF electrical and RF electromagnetic signals and supported in a position spaced from the major face of the substrate operatively coupled to the transducer. The directing assembly may be supported by the substrate in spaced relationship from the transducer and configured to direct EM energy in a region including the transducer and along a line extending away from the transducer and transverse to a plane of the major face.