A connection member according to an embodiment includes a dielectric material, a penetrating via penetrating through the dielectric material, a first metal plane provided in the dielectric material, the first metal plane being perpendicular to an extension direction of the penetrating via, the first metal plane crossing the penetrating via, and a second metal plane provided n or on the dielectric material in parallel with the extension direction of the penetrating via, the second metal plane connected to the first metal plane.

A module includes a substrate, a component mounted on a top surface that is one principal surface of the substrate, a first shielding film provided on a top surface and a side surface of the component, a sealing resin provided on the top surface of the substrate and seals the component, and a second shielding film provided on a top surface of the sealing resin. A hole is provided on a top surface of the sealing resin, to reach at least a part of the first shielding film. The second shielding film disposed in the hole is brought into contact with the first shielding film at positions facing a top surface and a side surface of the component.

An electronic assembly includes a first wafer including a stack of alternating first dielectric layers and first circuit layers, a flexible structure including a second dielectric layer and a second circuit layer covered by the second dielectric layer, and a second wafer stacked upon the first wafer and including chip packages arranged in an array. The flexible structure includes a first region embedded in the first wafer and a second region connected to the first region and extending out from an edge of the first wafer. The chip packages are electrically coupled to the second circuit layer of the flexible structure through the first circuit layers of the first wafer.

An electronic assembly includes a first wafer including a stack of alternating first dielectric layers and first circuit layers, a flexible structure including a second dielectric layer and a second circuit layer covered by the second dielectric layer, and a second wafer stacked upon the first wafer and including chip packages arranged in an array. The flexible structure includes a first region embedded in the first wafer and a second region connected to the first region and extending out from an edge of the first wafer. The chip packages are electrically coupled to the second circuit layer of the flexible structure through the first circuit layers of the first wafer.

An electronic component includes: an insulating substrate including a first main surface and a second main surface opposite to each other in a thickness direction and a side surface with a plurality of ground electrodes exposed thereto; conductive films each covering a surface of a corresponding one of the plurality of ground electrodes exposed to the side surface of the insulating substrate; and a shielding film covering the first main surface and the side surface of the insulating substrate and surfaces of the conductive films. The plurality of ground electrodes includes a first ground electrode and a second ground electrode, the first ground electrode and the second ground electrode being exposed to the side surface of the insulating substrate at a position closest to the first main surface and at a position closest to the second main surface, respectively.

An assembly comprises a circuit board structure and a plurality of connection portions. The circuit board structure has a main circuit board and a supplemental circuit board. The main circuit board is formed with an accommodating portion. The accommodating portion is recessed downward in an up-down direction from an upper surface of the main circuit board. The main circuit board has a plurality of upper main conductive portions which are formed on the upper surface of the main circuit board. The supplemental circuit board has a plurality of upper supplemental conductive portions which are formed on an upper surface of the supplemental circuit board. The supplemental circuit board is, at least in part, accommodated in the accommodating portion. Each of ones of the connection portions connects a respective one of the upper main conductive portions and a respective one of the upper supplemental conductive portions with each other.

A semiconductor package comprises an integrated circuit comprising a first connection terminal and a second connection terminal; an encapsulant encapsulating at least part of the integrated circuit; a first metal layer and a second metal layer. The first metal layer is placed upon at least a portion of one of the side walls of the encapsulant. The first metal layer is electrically connecting the first connection terminal and is configured to form an electrically conductive and mechanically stable connection with a metal trace of a base plate when mounting the semiconductor package to the base plate. The second metal layer is placed upon at least a portion of one or both of the first main surface and the second main surface of the encapsulant.

Electronic assemblies and methods of joining components are described. The electronic assemblies may include a bottom component with one or more pins mounted over a top component with one or more recesses, where the pins of the bottom component align with the recesses of the top component. Further, the recesses and pins may be structured so that the shape of the pins matches the shape of the recesses, and that the recesses at least partially surround the pins.