A method of producing an electrical through connection. A cut extending from a first surface to a second surface and separating the area into a first part and a second part is provided on an area of the flexible substrate. At least one of the first and second part is raised from a first plane of the first surface. A first wet conductive layer is printed on the first surface on and around the cut. The first wet layer is solidified into a first dried conductive layer. At least one of the first part and the second part is raised from a second plane of the second surface. A second wet conductive layer is printed on the second surface on and around the cut. The second wet conductive layer is solidified into a second dried conductive layer, which creates an electrical through connection with the first dried conductive layer.

A method of producing an electrical through connection. A cut extending from a first surface to a second surface and separating the area into a first part and a second part is provided on an area of the flexible substrate. At least one of the first and second part is raised from a first plane of the first surface. A first wet conductive layer is printed on the first surface on and around the cut. The first wet layer is solidified into a first dried conductive layer. At least one of the first part and the second part is raised from a second plane of the second surface. A second wet conductive layer is printed on the second surface on and around the cut. The second wet conductive layer is solidified into a second dried conductive layer, which creates an electrical through connection with the first dried conductive layer.

An interposer includes an interposer substrate having a series of vias, and a series of metallic interconnects in the series of vias. The interposer substrate has a first surface and a second surface opposite the first surface. The interposer substrate includes a dielectric material. A first pitch of the series of vias at a first end of the series of vias is different than a second pitch of the series of vias at a second end of the series of vias.

A method of manufacturing a through-hole electrode substrate includes forming a plurality of through-holes in a substrate, forming a plurality of through-hole electrodes by filling a conductive material into the plurality of through-holes, forming a first insulation layer on one surface of the substrate, forming a plurality of first openings which expose the plurality of through-hole electrodes corresponding to each of the plurality of through-hole electrodes, on the first insulation layer and correcting a position of the plurality of first openings using the relationship between a misalignment amount of a measured distance value of an open position of a leaning through-hole among the plurality of through-holes and of a design distance value of the open position of the leaning through-hole among the plurality of through-holes with respect to a center position of the substrate.

The disclosure is and includes at least an apparatus, system and method for a ramped electrical interconnection for use in semiconductor fabrications. The apparatus, system and method includes at least a first semiconductor substrate having thereon a first electrical circuit comprising first electrical components; a second semiconductor substrate at least partially covering the first electrical circuit, and having thereon a second electrical circuit comprising second electrical components; a ramp formed through the second semiconductor substrate between at least one of the first electrical components and at least one of the second electrical components; and an additively manufactured conductive trace formed on the ramp to electrically connect the at least one first electrical component and the at least one second electrical component.

A printed wiring board includes a dielectric layer, a first and second conductor layer, and a plurality of via conductors. The dielectric layer has first and second opposing surfaces. The first and second conductor layer lie in the first second surfaces of the dielectric layer, respectively. Each via conductor extends through the dielectric layer and connects the first and second conductor layers to each other. Part of the printed wiring board is surrounded with the via conductors and is an overlap between the first conductor layer and the second conductor layer in a transparent plan view. When viewed in plan, the via conductors each have an aspect ratio greater than 1 and a major axis extending in a first direction and a minor axis extending in a second direction. The via conductors include a via conductor whose major axis extends and connects the via conductors arranged in a line.

A printed circuit board comprises a substrate as well as resistors and electrical connections disposed on the substrate. The substrate couples to a video graphics array connector that has pins, including video pins and return pins. A video pin transmits a video signal, and a return pin provides a ground for a corresponding video pin. The substrate has openings, where each opening can receive a pin. The resistors and the electrical connections couple to a subset of the pins to mimic an external video graphics array monitor. The resistors comprise: a red connection resistor that can couple a red video pin with a red return pin; a green connection resistor that can couple a green video pin with a green return pin; and a blue connection resistor that can couple a blue video pin with a blue return pin.

In a flexible printed wiring board (1), a first electrical conduction pattern (4) prepared on the first surface (3a) on which a bare chip (2) is mounted is prepared only inside a mounting region (3c) of the bare chip. Preferably, the first electrical conduction patterns (4) are prepared so as to avoid positions opposite to test electrodes (2b) which the bare chip comprises. Thereby, in the flexible printed wiring board used for mounting the bare chip, occurrence of malfunction resulting from electrical connection with a part other than a bump of the bare chip can be certainly prevented, and reliability of various devices using the bare chip can be improved.

A method of forming an multi-chip carrier that includes providing a trace structure using an additive forming method. The method includes forming a metal layer on a trace structure to provide electrically conductive lines. A dielectric material may then be formed on the electrically conductive lines to encapsulate a majority of the electrically conductive lines. The ends of the electrically conductive lines that are exposed through the upper surface of the dielectric material provide a top processor mount location and the ends of the electrically conductive lines that are exposed through the sidewalls of the dielectric material provide a sidewall processor mount location.

Pastes are disclosed that are configured to coat a passage of a substrate. When the paste is sintered, the paste becomes electrically conductive so as to transmit electrical signals from a first end of the passage to a second end of the passage that is opposite the first end of the passage. The metallized paste contains a lead-free glass frit, and has a coefficient of thermal expansion sufficiently matched to the substrate so as to avoid cracking of the sintered paste, the substrate, or both, during sintering.