Pastes are disclosed that are configured to coat a passage of a substrate. When the paste is sintered, the paste becomes electrically conductive so as to transmit electrical signals from a first end of the passage to a second end of the passage that is opposite the first end of the passage. The metallized paste contains a lead-free glass frit, and has a coefficient of thermal expansion sufficiently matched to the substrate so as to avoid cracking of the sintered paste, the substrate, or both, during sintering.

Pastes are disclosed that are configured to coat a passage of a substrate. When the paste is sintered, the paste becomes electrically conductive so as to transmit electrical signals from a first end of the passage to a second end of the passage that is opposite the first end of the passage. The metallized paste contains a lead-free glass frit, and has a coefficient of thermal expansion sufficiently matched to the substrate so as to avoid cracking of the sintered paste, the substrate, or both, during sintering.

A method of forming an multi-chip carrier that includes providing a trace structure using an additive forming method. The method includes forming a metal layer on a trace structure to provide electrically conductive lines. A dielectric material may then be formed on the electrically conductive lines to encapsulate a majority of the electrically conductive lines. The ends of the electrically conductive lines that are exposed through the upper surface of the dielectric material provide a top processor mount location and the ends of the electrically conductive lines that are exposed through the sidewalls of the dielectric material provide a sidewall processor mount location.

Disclosed is a device for electrically connecting components, which device has at least one electrically insulating layer structure, at least one electrically conducting layer structure, which is stacked and consolidated with the at least one electrically insulating layer structure under formation of a stack of layers, and a warpage stabilization structure for stabilizing the device in a warpage-suppressing manner, which structure at least partially pervades layer structures of the stack of layers.

Described examples include a method of fabricating a gas cell, including forming a cavity in a first substrate, providing a nonvolatile precursor material in the cavity of the first substrate, bonding a second substrate to the first substrate to form a sealed cavity including the nonvolatile precursor material in the cavity, and activating the precursor material after or during forming the sealed cavity to release a target gas inside the sealed cavity.

An interposer for an electronic package including at least one angled via. The interposer can include a dielectric layer including a first surface and a second surface. The dielectric layer can include a normal axis perpendicular with the first or second surface. In an example, an angled via can include a first end located along the first surface and a second end located along the second surface. A longitudinal axis of the angled via can be extended between the first end and the second end. The longitudinal axis is disposed at an angle from the normal axis to form an angled via.

Described examples include a method of fabricating a gas cell, including forming a cavity in a first substrate, providing a nonvolatile precursor material in the cavity of the first substrate, bonding a second substrate to the first substrate to form a sealed cavity including the nonvolatile precursor material in the cavity, and activating the precursor material after or during forming the sealed cavity to release a target gas inside the sealed cavity.

Provided is a semiconductor device enabling highly accurate adjustment of a mounting height at a time when the semiconductor device is mounted on an assembly board, and an electronic apparatus. A linear lead is extracted from a bottom surface of a cylindrical resin sealing body covering a semiconductor chip, and a plurality of helical leads are arranged so as to wind around the linear lead, to thereby form a multi-helical structure. The plurality of helical leads forming the multi-helical structure has the same pitch.

A method of forming an multi-chip carrier that includes providing a trace structure using an additive forming method. The method includes forming a metal layer on a trace structure to provide electrically conductive lines. A dielectric material may then be formed on the electrically conductive lines to encapsulate a majority of the electrically conductive lines. The ends of the electrically conductive lines that are exposed through the upper surface of the dielectric material provide a top processor mount location and the ends of the electrically conductive lines that are exposed through the sidewalls of the dielectric material provide a sidewall processor mount location.

Provided is a semiconductor device enabling highly accurate adjustment of a mounting height at a time when the semiconductor device is mounted on an assembly board, and an electronic apparatus. A linear lead is extracted from a bottom surface of a cylindrical resin sealing body covering a semiconductor chip, and a plurality of helical leads are arranged so as to wind around the linear lead, to thereby form a multi-helical structure. The plurality of helical leads forming the multi-helical structure has the same pitch.