A multi-layer ceramic electronic component includes: a ceramic body including internal electrodes laminated in one axial direction and having a main surface facing in the one axial direction; and an external electrode including a base layer including a step portion formed on the main surface, and a plated layer formed on the base layer, the external electrode being connected to the internal electrodes.

The disclosure is and includes at least an apparatus, system and method for a ramped electrical interconnection for use in semiconductor fabrications. The apparatus, system and method includes at least a first semiconductor substrate having thereon a first electrical circuit comprising first electrical components; a second semiconductor substrate at least partially covering the first electrical circuit, and having thereon a second electrical circuit comprising second electrical components; a ramp formed through the second semiconductor substrate between at least one of the first electrical components and at least one of the second electrical components; and an additively manufactured conductive trace formed on the ramp to electrically connect the at least one first electrical component and the at least one second electrical component.

A component-embedded substrate includes: insulating layers each including a wiring pattern; an embedded component including a connection terminal; a plurality of vias that electrically connect the connection terminal to the wiring patterns adjacent to each other in a lamination direction. Each of the vias is composed of a via hole in the insulating layer and a conductive material in the via hole. One of the vias is a connection via connected to the connection terminal, and another of the vias is an adjacent via adjacent to the connection via in the lamination direction. The connection via and adjacent via overlap in a plan view. S1/A1≤0.61 and S1/A2≤0.61 are satisfied, where A1 is an average cross-sectional area of the connection via, A2 is an average cross-sectional area of the adjacent via, and S1 is an overlapping area of the connection via and adjacent via in the plan view.

An electroplating method of a circuit board includes: providing a multi-layer board having a conductive layer embedded therein; penetratingly forming a thru-hole and at least one penetrating hole in the multi-layer board, and forming a conductive portion on an inner wall defining the thru-hole and connected to the conductive layer, wherein the at least one penetrating hole is located at one side of the thru-hole, and an annular portion of the conductive layer exposed from the at least one penetrating hole is defined as an electroplated region; and electroplating the electroplated region to be formed with a metal post by applying a current to the conductive portion, wherein the metal post is filled in the at least one penetrating hole and is connected to the electroplated region.

A method includes providing an electrically conductive layer structure on top of an electrically insulating layer structure, forming a window in the electrically conductive layer structure and removing material of the electrically insulating layer structure below the window by a first laser beam, and subsequently removing further material of the electrically insulating layer structure below the window by a second laser beam having a smaller size than a size of the window.

A component carrier includes an electrically insulating layer structure having a first main surface and a second main surface with a through hole extending through the electrically insulating layer structure between the first main surface and the second main surface. An electrically conductive bridge structure connects opposing sidewalls of the electrically insulating layer structure delimiting the through hole. A vertical thickness of the electrically insulating layer structure is not more than 200 μm and a narrowest vertical thickness of the bridge structure is at least 20 μm.

A component carrier includes an electrically insulating layer structure, a first electrically conductive layer structure, a second electrically conductive layer structure, and a laser through-hole with an electrically conductive medium filling at least part of the through-hole. The first electrically conductive layer structure covers a first side of the electrically insulating layer structure and has a first window extending through the first electrically conductive layer structure formed by etching using a conformal mask. The second electrically conductive layer structure covers an opposed side of the electrically insulating layer structure and has a second window extending through the second electrically conductive layer structure formed by etching using a conformal mask. The laser through-hole extends through the electrically insulating layer structure. At least a portion of at least one sidewall of the electrically conductive layer structures delimiting the windows is tapered.

A component carrier includes a stack with at least one electrically conductive layer structure and at least one electrically insulating layer structure, a component embedded in the stack, and a via formed in the at least one electrically insulating layer structure along a horizontal path having a length being larger than a horizontal width.

A display device includes: a substrate having a first surface, a second surface opposite to the first surface, and an inner side surface defining through holes; a first wiring and a second wiring disposed on the first surface; and a first conductor and a second conductor disposed in one of the through holes. The first conductor is connected to the first wiring, the second conductor is connected to the second wiring, and the first and second conductors are insulated from each other.

A printed circuit board includes a first voltage plane disposed on a first surface of a first electrically insulating layer and a second voltage plane. An inter-layer slot that is formed through the first electrically insulating layer and includes an electrically conductive material electrically couples the first voltage plane to the second voltage plane.