A module includes a substrate, a component mounted on a top surface that is one principal surface of the substrate, a first shielding film provided on a top surface and a side surface of the component, a sealing resin provided on the top surface of the substrate and seals the component, and a second shielding film provided on a top surface of the sealing resin. A hole is provided on a top surface of the sealing resin, to reach at least a part of the first shielding film. The second shielding film disposed in the hole is brought into contact with the first shielding film at positions facing a top surface and a side surface of the component.

An integrated silicone for protecting electronic devices includes a base resin, a thermal initiator, and a photoinitiator.

A high voltage inductive adder is disclosed. An inductive adder may include a plurality of switch boards that each include a plurality of switch boards that include a plurality of solid state switches. These switch boards may be stacked one upon another. The inductive adder may include a transformer comprising a plurality of toroid-shaped transformer cores disposed on a corresponding one of the plurality of switch boards; and a transformer rod that extends through the plurality of switch boards and the plurality of transformer cores. The inductive adder may include an output electrically coupled with the transformer rod. And each of the plurality of circuit boards, for example, may include a tailbiter circuit electrically coupled in parallel with the output.

A chip resistor with a reduced thickness is provided. The chip resistor includes an insulating substrate, a resistor embedded in the substrate, a first electrode electrically connected to the resistor, and a second electrode electrically connected to the resistor. The first electrode and the second electrode are spaced apart from each other in a lateral direction that is perpendicular to the thickness direction of the substrate.

An embedded package structure includes an insulation substrate, a first conductive layer, a second conductive layer, an electronic component and a passive component. The insulation substrate has a first conductive via and a second conductive via. The first conductive layer is formed on a top surface of the insulation substrate and contacted with the first conductive via. The second conductive layer is formed on a bottom surface of the insulation substrate, and contacted with the second conductive via. The electronic component is embedded within the insulation substrate. Moreover, plural conducting terminals of the electronic components are electrically connected with the first conductive layer and the second conductive layer through the first conductive via and the second conductive via. The passive component is located near a first side of the electronic component and separated from the electronic component. The passive component is at least partially embedded within the insulation substrate.

Systems and methods for sense resistors are disclosed. In one aspect, an integrated sense resistor includes a plurality of first metal bumps alternating with a plurality of second metal bumps in at least a first lateral direction and a plurality of thin film resistors each disposed between and electrically connected to a pair of adjacent ones of first and second metal bumps. The integrated sense resistor can be configured for sensing a voltage developed by current flowing across the integrated sense resistor for determining a value of the current.

There is provided a solder alloy in which 0.5 mass % or more and 1.25 mass % or less of Sb, In satisfying the following formula (I) or (II) when [Sb] is set as a Sb content percentage (mass %) and [In] is set as an In content percentage (mass %): in a case of 0.5≦[Sb]≦1.0, 5.5≦[In]≦5.50+1.06[Sb] . . . (I), in a case of 1.0<[Sb]≦1.25, 5.5≦[In]≦6.35+0.212[Sb] . . . (II) (in the formula, [Sb] indicates a Sb content percentage (mass %) and [In] indicates an In content percentage (mass %)), 0.5 mass % or more and 1.2 mass % or less of Cu, 0.1 mass % or more and 3.0 mass % or less of Bi, 1.0 mass % or more and 4.0 mass % or less of Ag, and 0 mass % or more and 0.025 mass % or less of Co are contained, and has the remainder consisting essentially of Sn.

A multi-piece wiring substrate includes a matrix substrate including first and second insulating layers, and interconnection substrate regions arranged in a matrix. The matrix substrate includes dividing grooves opposing each other and disposed along boundaries between the interconnection substrate regions, and through-holes penetrating the matrix substrate in a thickness direction at positions where the dividing grooves are disposed. The inner surface conductor gradually decreases in thickness from a thick portion in a middle of the inner surface conductor, to thin portions disposed on a side of a boundary between the first and second insulating layers and on a first main surface side, and includes inclination portions each of which gradually increases in thickness from a boundary between corresponding one of the dividing grooves and the inner surface conductor to an inner surface of the inner surface conductor, in vertical sectional view.

An inrush current limiting circuit in aspects of the present disclosure may have one or more of the following features: a printed circuit board, an electrical input disposed on the circuit board, one or more electrical outputs disposed on the circuit board, a current limiting circuit connected between the electrical input and the one or more electrical outputs, at least one microcontroller connected within the current limiting circuit, at least one current sensor connected within the current limiting circuit, one or more current limiting components within the current limiting circuit for increasing voltage and current over time from the electrical input to the one or more electrical outputs by operation of the current sensor and the microcontroller.

A printed circuit board according to an embodiment includes: a first insulating portion having a cavity; a second insulating portion disposed on the first insulating portion; a third insulating portion disposed under the first insulating portion; and an electronic device disposed in the cavity, wherein a number of layers of the second insulating portion is different from a number of layers of the third insulating portion, and has an asymmetric structure with respect to the first insulating portion in which the electronic device is disposed.