A module includes a substrate having main surfaces; components mounted on at least one main surface of the substrate; a sealing resin on a surface of the substrate to embed the components; and a shielding film containing Cu as a main component and covering a top surface and at least one side surface of the sealing resin, wherein a surface of the shielding film is directly covered by a first Ni layer containing Ni—B or Ni—N as a main component, and a surface of the first Ni layer is covered by a second Ni layer containing Ni—P as a main component.

The present invention provides for a method and structure for forming three-dimensionally routed dielectric wires between discrete points on the two or more parallel circuit planes. The wires may be freely routed in three-dimensional space as to create the most efficient routing between the two arbitrarily defined points on the two or more parallel circuit planes. Metalizing the outer surfaces of these three dimensional dielectric wires electrically coupling the discrete wires to their respective discrete contact points. Two or more of these wires may be in intimate contact to one another electrically coupling to each other as well as to two or more discrete contact pads. These electrically coupled contact pads may be on opposite sides or on the same side of the structure and the formed metalized wires may originate on one side and terminate on the other or originate and terminate from the same side

Embodiments include a microelectronic device package structure having an inductor within a portion of a substrate, wherein a surface of the inductor is substantially coplanar with a surface of the substrate. One or more thermal interconnect structures are on the surface of the inductor. A conductive feature is embedded within a board, where a surface of the conductive feature is substantially coplanar with a surface of the board. One or more thermal interconnect structures are on the surface of the conductive feature of the board, where the thermal interconnect structures provide a thermal pathway for cooling for the inductor.

The disclosure specifies a circuit arrangement having electronic first components arranged on a circuit board and lying at high-voltage potential. The circuit arrangement includes functionless, electronic second components lying at high-voltage potential, which are arranged on the circuit board adjacent to the electronic first components, and configured to reduce the maximum electrical field strength between the first components and a reference potential and/or between pads of the circuit board and the reference potential. Through the additional, functionless components, the maximum electrical field strength between electronic components at high voltage and at a reference potential will be reduced. The disclosure also specifies a high voltage generation unit and an x-ray generator.

A device includes a printed circuit board assembly having a printed circuit board and one or more electronic components disposed on the printed circuit board, and a nanofilm disposed on the printed circuit board assembly. The nanofilm includes an inner coating in contact with the printed circuit board assembly, the inner coating including metal oxide nanoparticles having a particle diameter in a range of 5 nm to 100 nm; and an outer coating in contact with the inner coating, the outer coating including silicon dioxide nanoparticles having a particle diameter in a range of 0.1 nm to 10 nm.

A method of manufacturing a printed circuit board includes providing a printed circuit board (PCB) substrate including at least one insulating layer and first and second conductive layers separated from one another by the at least one insulating layer, forming a first via hole in the PCB substrate extending from the first conductive layer to the second conductive layer, where the first via hole is defined by a first sidewall of the PCB substrate, forming a second via hole in the PCB substrate, where the second via hole is defined by a second sidewall of the PCB substrate, and selectively plating the first sidewall and the second sidewall to form a first via and a second via, respectively, where the first via and the second via have different via sidewall thicknesses.

A transformer is configured to include a pair of cores and that each have an inner leg, wherein a primary winding that is wound around a bobbin having a hollow into which the inner legs of the cores and are inserted, and a secondary winding that has a hollow into which the inner legs of the cores and are inserted and that is constituted of a conductor formed by die-cutting a metal plate into a ring, are dispersedly arranged over the inner legs of the cores and. The bobbin has bobbin support portions that come into contact with a surface of a printed circuit board on which the transformer is implemented.

A circuit including a die and an integrated passive device. The die includes a first substrate and at least one active device. The integrated passive device includes a first layer, a second substrate, a second layer and an inductance. The inductance includes vias, where the vias are implemented in the second substrate. The inductance is implemented on the first layer, the second substrate, and the second layer. A resistivity per unit area of the second substrate is greater than a resistivity per unit area of the first substrate. The third layer is disposed between the die and the integrated passive device. The third layer includes pillars, where the pillars respectively connect ends of the inductance to the at least one active device. The die, the integrated passive device and the third layer are disposed relative to each other to form a stack.

A metal member includes a plate-shaped portion provided on an upper main surface of a substrate, and includes a front main surface and a back main surface arranged in a front-back direction when viewed in an up-down direction. A first electronic component is mounted on the upper main surface of the substrate and is disposed in front of the metal member. A second electronic component is mounted on the upper main surface of the substrate and is disposed behind the metal member. A sealing resin layer is provided on the upper main surface of the substrate and covers the metal member and the one or more electronic components. The plate-shaped portion is provided with one or more upper notches extending downward from the upper side. The metal member further includes one or more foot portions extending forward or backward from the lower side.

An embodiment of the invention may include a method, and resulting structure, of forming a semiconductor structure. The method may include forming a component hole from a first surface to a second surface of a base layer. The method may include placing an electrical component in the component hole. The electrical component has a conductive structure on both ends of the electrical component. The electrical component is substantially parallel to the first surface. The method may include forming a laminate layer on the first surface of the base layer, the second surface of the base layer, and between the base layer and the electrical component. The method may include creating a pair of via holes, where the pair of holes align with the conductive structures on both ends of the electrical component. The method may include forming a conductive via in the pair of via holes.