An array circuit board 11B includes a glass substrate, an IC chip 20, two ACFs 30, and a resin film 32. The IC chip 20 is disposed on the glass substrate. The ACFs 30 are disposed between the glass substrate and the IC chip 20 for electrically connecting the glass substrate and the IC chip 20 together. The ACFs 30 are separated from each other. The resin film 32 is made of resin material having cure shrinkage smaller than the ACFs 30 and disposed to fill a gap between the ACFs 30 adjacent to each other between the glass substrate and the IC chip 20.

In a high frequency signal line, a first signal line extends along a first dielectric element assembly, a first reference ground conductor extends along the first signal line, a second signal line is provided in or on the second dielectric element assembly and extends along the second dielectric element assembly, a second reference ground conductor is provided in or on the second dielectric element assembly and extends along the second signal line. A portion of a bottom surface at an end of the first dielectric element assembly and a portion of the top surface at an end of the second dielectric element assembly are joined together such that a joint portion of the first and second dielectric element assemblies includes a corner. The second signal line and the first signal line are electrically coupled together. The first and second reference ground conductors are electrically coupled together.

Surge arrester for a an electric machine, comprising a dummy component (2) which is, compared to components on a circuit board (1) of the electric machine, mounted at the shortest distance from a discharge element (4) of the electric machine, the dummy component (2) being connected to earth potential in at least one terminal.

A semiconductor substrate includes: 1) a first dielectric structure having a first surface and a second surface opposite the first surface; 2) a second dielectric structure having a third surface and a fourth surface opposite the third surface, wherein the fourth surface faces the first surface, the second dielectric structure defining a through hole extending from the third surface to the fourth surface, wherein a cavity is defined by the through hole and the first dielectric structure; 3) a first patterned conductive layer, disposed on the first surface of the first dielectric structure; and 4) a second patterned conductive layer, disposed on the second surface of the first dielectric structure and including at least one conductive trace. The first dielectric structure defines at least one opening to expose a portion of the second patterned conductive layer.

A component-embedded substrate includes a multilayer body formed by stacking up a plurality of resin layers in a predetermined direction, a component embedded in the multilayer body, the component having a plurality of terminal electrodes, a plurality of joining conductors provided in the multilayer body and joined to the plurality of terminal electrodes, a plurality of wiring conductors provided in the multilayer body and electrically coupled to the plurality of joining conductors and at least one auxiliary member enclosed within an outer boundary of the component provided in the multilayer body. The auxiliary member may be electrically insulated from each of the plurality of wiring conductors and arranged to balance pressures acting on the plurality of terminal electrodes when pressure is applied on the multilayer body.

A carrier substrate includes an insulation encapsulation, first conductive patterns, second conductive patterns, at least one first dummy pattern, and at least one second dummy pattern. The carrier substrate has a first layout region and a second layout region. The first conductive patterns and the first dummy pattern are located in the first layout region. The second conductive patterns and the second dummy pattern are located in the second layout region. The first and second conductive patterns and the first and second dummy patterns are embedded in the insulation encapsulation. The insulation encapsulation exposes top surfaces of the first and second conductive patterns and the first and second dummy patterns. The first dummy pattern and the second dummy pattern are insulated from the first conductive patterns and the second conductive patterns. An edge profile of the first dummy pattern facing the second dummy pattern is non-linear.

The present disclosure relates to a semiconductor substrate, a semiconductor module and a method for manufacturing the same. The semiconductor substrate includes a first dielectric structure, a second dielectric structure, a first patterned conductive layer and a second patterned conductive layer. The first dielectric structure has a first surface and a second surface opposite the first surface. The second dielectric structure has a third surface and a fourth surface opposite the third surface, where the fourth surface is adjacent to the first surface. The second dielectric structure defines a through hole extending from the third surface to the fourth surface. A cavity is defined by the through hole and the first dielectric structure. The first patterned conductive layer is disposed on the first surface of the first dielectric structure. The second patterned conductive layer is disposed on the second surface of the first dielectric structure.

The present disclosure relates to a semiconductor substrate, a semiconductor module and a method for manufacturing the same. The semiconductor substrate includes a first dielectric structure, a second dielectric structure, a first patterned conductive layer and a second patterned conductive layer. The first dielectric structure has a first surface and a second surface opposite the first surface. The second dielectric structure has a third surface and a fourth surface opposite the third surface, where the fourth surface is adjacent to the first surface. The second dielectric structure defines a through hole extending from the third surface to the fourth surface. A cavity is defined by the through hole and the first dielectric structure. The first patterned conductive layer is disposed on the first surface of the first dielectric structure. The second patterned conductive layer is disposed on the second surface of the first dielectric structure.

An electronic control module includes a printed circuit board and an electrical component. The circuit board has a contact area arranged on a component side. The electrical component has an electrical connection element with a connection section running parallel to the component side and is electrically connected to the contact area. An adapter is arranged on the circuit board independently of the electrical component and has a holding body fastened to the circuit board outside the contact area and a metal web. The web is arranged on the holding body and has a contact section running parallel to the component side. The contact section and the connection section lie atop another and are welded to one another in a covering area. The web or the connection element makes electrical contact with the contact area by an electrically conductive material applied to the contact area.

Embodiments of the present disclosure are directed toward techniques and configurations for electrical signal absorption in an interconnect disposed in a printed circuit board (PCB) assembly. In one instance, a PCB assembly may comprise a substrate, and an interconnect formed in the substrate to route an electrical signal within the PCB. The interconnect may be coupled with a connecting component that is disposed on a surface of the PCB. An absorbing material may be disposed on the PCB to be in direct contact with at least a portion of the connecting component to at least partially absorb a portion of the electrical signal. Other embodiments may be described and/or claimed.