A collation system includes a first node, a second node and a third node. The first node includes: an encryption unit; a distance calculation unit t; and a collation data generation unit. The second node includes: a key generation unit; and a collation unit. The third node includes: a storage unit; and a collation information generation unit.

In one implementation, flash memory chips are provided with an operating power supply voltage to substantially match a power supply voltage expected at an edge connector of a dual inline memory module. The one or more of the flash memory chips and a memory support application integrated circuit (ASIC) may be mounted together into a multi-chip package for integrated circuits. The one or more flash memory chips and the memory support ASIC may be electrically coupled together by routing one or more conductors between each in the multi-chip package. The multi-chip package may be mounted onto a printed circuit board (PCB) of a flash memory DIMM to reduce the number of packages mounted thereto and reduce the height of the flash memory DIMM. The number of printed circuit board layers may also be reduced, such as by integrating address functions into the memory support ASIC.

Techniques and mechanisms for controlling configurable circuitry including an antifuse. In an embodiment, the antifuse is disposed in or on a substrate, the antifuse configured to form a solder joint to facilitate interconnection of circuit components. Control circuitry to operate with the antifuse is disposed in, or at a side of, the same substrate. The antifuse is activated based on a voltage provided at an input node, where the control circuitry automatically transitions through a pre-determined sequence of states in response to the voltage. The pre-determined sequence of states coordinates activation of one or more fuses and switched coupling one or more circuit components to the antifuse. In another embodiment, multiple antifuses, variously disposed in or on the substrate, are configured each to be activated based on the voltage provided at an input node.

There is provided a semiconductor apparatus including: a memory operation terminal for inputting a first signal; a high-speed communication terminal for inputting a second signal to a high-speed communication controller; an inspection terminal for performing debugging; and a terminal mounting surface at which a plurality of coupling terminals including the memory operation terminal, the high-speed communication terminal, and the inspection terminal are provided, in which the terminal mounting surface includes a first side, a second side, a third side, and a fourth side, the plurality of coupling terminals include a first terminal row located adjacent to the third side and arranged from the first side toward the second side; the first terminal row includes a first inspection terminal among the plurality of inspection terminals, and the first inspection terminal is located closest to the first side in the first terminal row.

A chip component includes a chip component main body, an electrode pad formed on a top surface of the main body, a protective film covering the top surface of the main body and having a contact hole exposing the pad, and an external connection electrode electrically connected to the pad via the hole and having a protruding portion, which, in a plan view looking from a direction perpendicular to a top surface of the pad, extends to a top surface of the film and protrudes further outward than a region of contact with the pad over the full periphery of an edge portion of the hole. A method for manufacturing the component includes forming the pad on the main body's top surface, forming the protective film, forming the hole in the film so as to expose the pad, and forming the electrode electrically connected to the pad via the hole.

A field programmable solder BeTA (FPSBGA) module may be utilized to assemble PCB/Substrate in any stack-up configuration. The local field programmable soldering BGA includes control system provides the necessary feedback for effective control of thermal profiles. The FPSBGA enables a control component (110) to cause the execution of the temperature application component (120) to cause a non-uniform application of specified temperature parameters to the substrate.

A chip resistor has a substrate, a first connection electrode and a second connection electrode that are formed on the substrate, and a resistor network that is formed on the substrate and that has ends one of which is connected to the first connection electrode and the other one of which is connected to the second connection electrode. The resistor network is provided with a resistive circuit. The resistive circuit has a resistive element film line that is provided along inner wall surfaces of trenches. The resistive element film line extending along the inner wall surfaces of the trenches is long and has a high resistivity as a unit resistive element.

A method of making an electronic device includes forming an electrically conductive pattern on a substrate, forming a cover layer on the substrate and the electrically conductive pattern, and forming openings in the cover layer and being aligned with the electrically conductive pattern. The method also includes positioning an IC on the cover layer so that bond pads of the IC are aligned with the openings, and heating under pressure the cover layer to both mechanically secure and electrically interconnect the IC.

The invention provides transient devices, including active and passive devices that physically, chemically and/or electrically transform upon application of at least one internal and/or external stimulus. Incorporation of degradable device components, degradable substrates and/or degradable encapsulating materials each having a programmable, controllable and/or selectable degradation rate provides a means of transforming the device. In some embodiments, for example, transient devices of the invention combine degradable high performance single crystalline inorganic materials with selectively removable substrates and/or encapsulants.

A chip component includes a substrate, an element circuit network including a plurality of element parts formed on the substrate, an external connection electrode provided on a surface of the substrate to provide external connection for the element circuit network, a plurality of fuses formed on the substrate and disconnectably connecting each of the plurality of element parts to the external connection electrode, a solder layer formed on an external connection terminal of the external connection electrode and a resin film which covers the surface of the substrate and other surface which intersects the surface of the substrate.