Embodiments of the present disclosure are directed towards techniques and configurations for dual surface finish package substrate assemblies. In one embodiment a method includes depositing a first surface finish on one or more electrical routing features located on a first side of a package substrate and on one or more lands located on a second side of the package substrate, the second side being opposite the first side of the substrate. The method may further include removing the first surface finish on the first side of the package substrate; and depositing a second surface finish on the one or more electrical routing features of the first side. The depositing of the second surface finish may be accomplished by one of a Direct Immersion Gold (DIG) process or an Organic Solderability Preservative (OSP) process. Other embodiments may be described and/or claimed.

A wiring board with a cavity for a built-in electronic component includes a conductor layer including a conductor circuit layer and a plane layer, and an insulating layer laminated on the conductor layer and having a cavity such that the cavity is forming an exposed portion of the plane layer and formed to mount a built-in electronic component on the exposed portion of the plane layer. The plane layer has a recess structure formed in an outer peripheral portion in the exposed portion of the plane layer.

An electrical connector assembly includes a carrier having an upper surface and a lower surface. The carrier includes a plurality of contact openings therethrough. The electrical connector assembly includes contacts coupled to the carrier and passing through the corresponding contact openings. Each contact has a conductive polymer column extending between an upper mating interface and a lower mating interface. The conductive polymer column includes an inner core manufactured from a first material and an outer shell manufactured from a second material. The second material has a higher electrical conductivity than the first material. The first material has a lower compression set than the second material.

A method of manufacturing an interposer substrate, including providing a carrier having a first circuit layer formed thereon, forming a plurality of conductive pillars on the first circuit layer, forming a first insulating layer on the carrier, with the conductive pillars being exposed from the first insulating layer, forming on the conductive pillars a second circuit layer that is electrically connected to the conductive pillars, forming a second insulating layer on the second surface of the first insulating layer and the second circuit layer, exposing a portion of a surface of the second circuit layer from the second insulating layer, and removing the carrier. The invention further provides the interposer substrate as described above.

A multilayer ceramic capacitor includes a capacitor main body including a multilayer body including dielectric layers and internal electrode layers alternately laminated, and external electrodes each at end surfaces of the multilayer body and connected to the internal electrode layers, and two interposers on a surface in a lamination direction of the capacitor main body, and spaced apart from each other in a length direction connecting the two end surfaces and intersecting the lamination direction. The external electrodes each include a bulge portion protruding in the lamination direction on the surface of the capacitor main body. The interposers each include a recess portion on each of the end surfaces, and in a cross section extending in the lamination direction and the length direction and passing through a center in a width direction. The bulge portion is closer to the end surface in the length direction than the recess portion.

Space transformers, planarization layers for space transformers, methods of fabricating space transformers, and methods of planarizing space transformers are disclosed herein. In one embodiment, the space transformers include a space transformer assembly including a first rigid space transformer layer, a second rigid space transformer layer, and an attachment layer that extends between the first rigid space transformer layer and the second rigid space transformer layer. In another embodiment, the space transformers include a space transformer body and a flex cable assembly. The planarization layer includes an interposer, a resilient dielectric layer, a planarized rigid dielectric layer, a plurality of holes, and an electrically conductive paste extending within the plurality of holes. In one embodiment, the methods include methods of fabricating the space transformer assembly. In another embodiment, the methods include methods of planarizing a space transformer.

An interposer includes an interposer body; first and second lower patterns spaced apart from each other on a lower surface of the interposer body; and first and second upper patterns spaced apart from each other on an upper surface of the interposer body. The first and second upper patterns include first and second shape-securing layers spaced apart from each other on the upper surface of the interposer body, and first and second acoustic noise reduction layers disposed on the first and second shape-securing layers, respectively. An electronic component includes a capacitor and the interposer.

An electronic device including a shielding structure is provided. The electronic device includes a housing, a first board disposed in an inner space of the housing and including a first electrical element and a first ground layer, a second board disposed in the inner space to be spaced apart from the first board and including a second electrical element, and an interposer disposed between the first board and the second board so as to electrically connect the first board and the second board to each other. The second board includes a first surface facing the first board, a second surface facing away from the first surface, insulating layers disposed between the first surface and the second surface, first slits formed at a predetermined interval in a first conductive area disposed in a first insulating layer among the insulating layers, and second slits formed at a predetermined interval in a second conductive area disposed in a second insulating layer between the first insulating layer and the second surface. The first slits are disposed at a position where the plurality of first slits do not overlap the plurality of second slits in case the second board is viewed from above.

The invention relates to an electric interface, in particular an interposer, having a first connection plane with at least one first contact surface pair, each of which has a first and second contact surface, and a second connection plane with at least one second contact surface pair, each of which has a third and a fourth contact surface. For each of a first and second contact surface pair, a first electric connection electrically connects the first contact surface of the first connection plane to the third contact surface of the second connection plane, and a second electric connection electrically connects the second contact surface of the first connection plane to the fourth contact surface of the second connection plane. The first electric connection between the first and third contact surface has a specified first geometric length, and the second electric connection between the second and fourth contact surface has a specified second geometric length, the first and second geometric length being different.

A printed wiring board includes a support plate, and a build-up wiring layer including resin insulating layers and conductor layers and having a first surface and a second surface on the opposite side with respect to the first surface such that the support plate is positioned on the first surface of the build-up wiring layer. The resin insulating layers in the build-up wiring layer include a first resin insulating layer that forms the second surface of the build-up wiring layer, and the build-up wiring layer includes first conductor pads embedded in the first resin insulating layer such that each of the first conductor pads has an exposed surface exposed from the second surface of the build-up wiring layer.