A lamination circuit board structure lamination circuit board structure includes a printed circuit board substrate including conductive wiring traces on at least a first wiring face, a prepreg layer formed over the first wiring face, and a patch having an area smaller than 1,000 mm.sup.2. The patch includes conductive wiring traces formed on a wiring face and is laminated to the printed circuit board substrate over the prepreg layer, oriented with the wiring face in contact with and pressed into the prepreg layer. Portions of the prepreg layer fill interstices between the conductive wiring traces.

An article includes a solid circuit die on a first major surface of a substrate, wherein the solid circuit die includes an arrangement of contact pads, and wherein at least a portion of the contact pads in the arrangement of contact pads are at least partially exposed on the first major surface of the substrate to provide an arrangement of exposed contact pads; a guide layer including an arrangement of microchannels, wherein the guide layer contacts the first major surface of the substrate such that at least some microchannels in the arrangement of microchannels overlie the at least some exposed contact pads in the arrangement of exposed contact pads; and a conductive particle-containing liquid in at least some of the microchannels. Other articles and methods of manufacturing the articles are described.

A package carrier includes a substrate, at least one interposer disposed in at least one opening of the substrate, a conductive structure layer, a first build-up structure, and a second build-up structure. The interposer includes a glass substrate, at least one conductive via, at least one first pad, and at least one second pad. The conductive via passes through the glass substrate, and the first and the second pads are disposed respectively on an upper surface and a lower surface of the glass substrate opposite to each other and are connected to opposite ends of the conductive via. The conductive structure layer is disposed on the substrate and is structurally and electrically connected to the first and the second pads. The first and the second build-up structures are disposed respectively on the first and the second surfaces of the substrate and are electrically connected to the conductive structure layer.

The present invention relates to a method for preparing a patterned polyimide coverlay on a substrate. The method includes: providing a polyimide dry film including a carrier and a non-photosensitive polyimide layer on the carrier, the non-photosensitive polyimide layer containing (i) a polyimide precursor or soluble polyimide and (ii) a solvent; forming a predetermined pattern in the polyimide dry film; laminating the patterned polyimide dry film onto a substrate in such a manner that the non-photosensitive polyimide layer faces the substrate; and forming a patterned polyimide coverlay by heating.

A substrate structure, a manufacturing method thereof, and an electronic device. The substrate structure includes a substrate, conductive wires and conductive members. Multiple through holes penetrate through the substrate body of the substrate. Multiple first conductive pads are arranged on the first surface of the substrate body. Multiple second conductive pads are arranged on the second surface of the substrate body. The conductive wires are accommodated in the through holes and each has a first end in the first opening of corresponding through hole and a second end in the second opening of corresponding through hole. The conductive members are distributed on the first and second surfaces, and both ends thereof are connected to the corresponding first and second conductive pads through the conductive members. At least part of each conductive wire does not contact the hole wall of each through hole in a direct manner.

A multi-layer ceramic electronic component includes: a ceramic body including internal electrodes laminated in one axial direction and having a main surface facing in the one axial direction; and an external electrode including a base layer including a step portion formed on the main surface, and a plated layer formed on the base layer, the external electrode being connected to the internal electrodes.

A resin composition is provided and includes (A) a modified polyphenylene ether compound terminal-modified with a substituent having a carbon-carbon unsaturated double bond, (B) a maleimide compound containing no phenylmaleimide group and having a hydrocarbon group having 10 or more carbon atoms in the molecule thereof, and (C) at least one selected from a maleimide compound containing a phenylmaleimide group and a maleimide compound having an aliphatic hydrocarbon group having 9 or less carbon atoms in the molecule thereof, in which the content ratio of the component (A) to the component (B) is (A):(B)=20:80 to 90:10 in mass ratio.

A method and structure for forming conductive structure such as an electric circuit, or a portion of an electric circuit, can include the use of a thermal print head and a ribbon including a carrier and a metal layer. The thermal print head is used to print a first portion of the metal layer onto a sacrificial print medium. The first portion printed has a first pattern, where a second portion having a second pattern remains on the carrier. The first pattern is a reverse image at least a portion of the electric circuit, while the second pattern includes at least a portion of the electric circuit. The second portion having the second pattern can be transferred to a circuit substrate, then used as an electric circuit.

A patterned conductive article 200 includes a substrate 210 including a unitary layer 210-1 and includes a micropattern of conductive traces 220 embedded at least partially in the unitary layer. Each conductive trace extends along a longitudinal direction (y-direction) of the conductive trace and includes a conductive seed layer 230 having a top major surface 232 and an opposite bottom major surface 234 in direct contact with the unitary layer; and a unitary conductive body 240 disposed on the top major surface of the conductive seed layer. The unitary conductive body and the conductive seed layer differ in at least one of composition or crystal morphology. The unitary conductive body has lateral sidewalls 242, 244 and at least a majority of a total area of the lateral sidewalls is in direct contact with the unitary layer.

A method for manufacturing an electronic component by a pressure-assisted low-temperature sintering process, by using a pressure sintering device having an upper die and a lower die is disclosed. The upper the die and/or the lower die is provided with a first pressure pad, wherein the method includes the following steps: placing a first sinterable component on a first sintering layer provided on a top layer of a first substrate; joining the sinterable component and the top layer of the first substrate to form a first electronic component by pressing the upper die and the lower die towards each other, wherein the sintering device is simultaneously heated.