Patent classifications
H05K2203/016
LIGHTING ELEMENT ALIGNMENT
The invention refers to a method for assembling at least one lighting element onto a substrate, the method comprising: pre-assembling at least one lighting element onto a temporary carrier; pre-assembling at least one reference element onto the temporary carrier; aligning the pre-assembled temporary carrier onto the substrate based, at least in part, on the at least one reference element of the temporary carrier; and mounting the at least one lighting element onto the substrate. The invention further relates to substrate comprising: at least one lighting element, wherein the at least one lighting element is assembled onto the substrate, in particular by a method according to the first aspect of the present invention, and to a use of a method for assembling at least one lighting element onto a substrate.
Copper foil with carrier
An extremely thin copper foil with a carrier is provided that can keep stable releasability even after being heated for a prolonged time at a high temperature of 350° C. or more. The extremely thin copper foil with a carrier includes a carrier composed of a glass or ceramic material; an intermediate layer provided on the carrier and composed of at least one metal selected from the group consisting of Cu, Ti, Al, Nb, Zr, Cr, W, Ta, Co, Ag, Ni, In, Sn, Zn, Ga, and Mo; a release layer provided on the intermediate layer and including a carbon sublayer and a metal oxide sublayer or containing metal oxide and carbon; and an extremely thin copper layer provided on the release layer.
Circuit board structure and manufacturing method thereof
A circuit board structure includes a first dielectric layer, at least one first circuit layer, a second dielectric layer, and an insulating protection layer. The first circuit layer is mounted on the first dielectric layer, and includes at least one first circuit. The second dielectric layer is mounted on the first circuit layer, and includes at least one thermally conductive bump and at least one electrically conductive bump. The electrically conductive bump is electrically connected to the first circuit. The insulating protection layer is mounted on the second dielectric layer. The thermally conductive bump directly contacts the glass substrate. When lasering is applied to cut the glass substrate for de-bonding, the lasering heat energy can be absorbed and dissipated by the thermally conductive bump, resolving the problem of circuit de-bonding and raising the process yield. In addition, a manufacturing method of the circuit board structure is provided.
MULTILAYER BODY
There is provided a laminate in which a decrease in the release function of a release layer can be suppressed even when the laminate is heat-treated under either temperature condition of low temperature and high temperature. This laminate includes a carrier; an adhesion layer on the carrier and containing a metal M.sup.1 having a negative standard electrode potential; a release-assisting layer on a surface of the adhesion layer opposite to the carrier and containing a metal M.sup.2 (M.sup.2 is a metal other than an alkali metal and an alkaline earth metal); a release layer on a surface of the release-assisting layer opposite to the adhesion layer; and a metal layer on a surface of the release layer opposite to the release-assisting layer, and T.sub.2/T.sub.1, a ratio of a thickness of the release-assisting layer, T.sub.2, to a thickness of the adhesion layer, T.sub.1, is more than 1 and 20 or less.
METHOD FOR MANUFACTURING DEVICE CONNECTED BODY, AND DEVICE CONNECTED BODY
A method for manufacturing a device connected body, including: a step A for readying a first laminate having, in the order listed, an inorganic substrate, a resin layer, and a plurality of devices mounted on the resin layer so that a gap is present therebetween; a step B for forming, on the first laminate, an elastomer layer so as to cover the plurality of devices and the gap portion and obtaining a second laminate; and a step C for peeling the inorganic substrate. The resin layer is either formed as a plurality of resin layers in advance at least at positions corresponding to the plurality of devices, or formed as a plurality of resin layers at least at positions corresponding to the plurality of devices by removing a part of the resin layer after step C for peeling the inorganic substrate.
Composite layer circuit element and manufacturing method thereof
The embodiment of the disclosure provides a composite layer circuit element and a manufacturing method thereof. The manufacturing method of the composite layer circuit element includes the following. A carrier is provided. A first dielectric layer is formed on the carrier, and the first dielectric layer is patterned. The carrier on which the first dielectric layer is formed is disposed on a first curved-surface mold, and the first dielectric layer is cured. A second dielectric layer is formed on the first dielectric layer. The second dielectric layer is patterned. The carrier on which the first dielectric layer and the second dielectric layer are formed is disposed on a second curved-surface mold, and the second dielectric layer is cured. A thickness of a projection of the first curved-surface mold is smaller than a thickness of a projection of the second curved-surface mold.
Flexible electronic structure and method for producing same
A flexible electronic structure includes a first film, made of a first polymer or glass, and a second film, made of a second polymer, in which at least one electronic component is arranged. The second film covers the first film. The flexible electronic structure also includes at least one electrically conductive track arranged between the first film and the second film, and each electrically connected to one of the electronic components, by a respective interconnection element. Optionally, the flexible electronic structure includes a third film, made of a third polymer or glass, covering the second film. The interconnection element is arranged near the neutral plane of the structure, and the structure includes at least one compensation layer, so as to position the neutral plane at a desired location.
METHOD AND APPARATUS FOR EFFICIENT MANUFACTURE OF HIGH PERFORMANCE ELECTRONIC DEVICE WITH CABLED INTERCONNECTS
A subassembly for efficiently and reliably assembling a high performance electronic device. The electronic device may include numerous cabled interconnects in a subassembly that is subsequently mechanically and electrically connected to a PCB populated with high performance electronic components. First ends of cables in the cabled interconnects may be terminated by a first type of connector configured for connection to the PCB via a downward force. The second ends of the cables may be terminated with a second type of connectors that may make connections to other portions of an electronic system incorporating the electronic device. The connectors at the first ends of the cables may be releasably held within an organizer. The connectors may be simply mounted to the PCB by positioning the organizer with respect to the PCB, releasing the connectors from the organizer, and pushing the connectors into engagement with mounting locations on the PCB.
STRETCHABLE SENSOR AND METHOD OF MANUFACTURING THE SAME AND WEARABLE DEVICE
A stretchable sensor includes a stretchable layer including an elastomer, and a conductive layer at least partially buried in the stretchable layer and including a conductive nanostructure. The stretchable layer includes a plurality of first regions including a ferromagnetic material buried in the elastomer, and a second region excluding the plurality of first regions.
Semiconductor structures and methods
A method includes attaching a substrate to a carrier, aligning external connectors on a first surface of a first semiconductor package to first conductive pads on a first surface of the substrate facing away from the carrier, and performing a reflow process, where a difference in coefficients of thermal expansion (CTEs) between the substrate and the carrier causes a first shape for the first surface of the substrate during the reflow process, where differences among CTEs of materials of the first semiconductor package causes a second shape for the first surface of the first semiconductor package during the reflow process, and wherein the first shape substantially matches the second shape. The method further includes removing the carrier from the substrate after the reflow process.