A wiring circuit board includes a metal support layer, a base insulating layer disposed on one side in a thickness direction of the metal support layer, and a conductive layer disposed on one side in the thickness direction of the base insulating layer, and including a first terminal and a ground lead residual portion electrically connected to the first terminal. A thickness of the ground lead residual portion is thinner than a thickness of the first terminal.

A method of performing an immersion tin process in the production of a component carrier is provided which includes immersing at least a part of a copper surface of the component carrier in a composition containing Sn(II) in an immersion tin unit, while passing a non-oxidizing gas through the immersion tin unit, wherein at least part of the non-oxidizing gas is recycled. In addition, an apparatus for performing an immersion tin process in the production of a component carrier, a method of performing a copper plating process in the production of a component carrier and an apparatus for performing a copper plating process in the production of a component carrier are provided.

A multi-layer circuit board is formed multiple layers of a catalytic layer, each catalytic layer having an exclusion depth below a surface, where the cataltic particles are of sufficient density to provide electroless deposition in channels formed in the surface. A first catalytic layer has channels formed which are plated with electroless copper. Each subsequent catalytic layer is bonded or laminated to an underlying catalytic layer, a channel is formed which extends through the catalytic layer to an underlying electroless copper trace, and electroless copper is deposited into the channel to electrically connect with the underlying electroless copper trace. In this manner, traces may be formed which have a thickness greater than the thickness of a single catalytic layer.

A printed circuit board includes an insulating layer, a circuit pattern embedded in the insulating layer and including a first metal layer, a second metal layer and a third metal layer disposed between the first metal layer and the second metal layer, and a connection conductor disposed on one surface of the insulating layer and connected to the circuit pattern, wherein the first metal layer is exposed through the one surface of the insulating layer.

A method for manufacturing a printed circuit board includes forming a through hole in an insulating layer of the printed circuit board, filling the through hole by plating to form a plating layer on the insulating layer, and removing the plating layer from the insulating layer; and forming a circuit pattern on the insulating layer.

Light reflection from a metal mesh touch sensor is reduced or prevented by encasing the metal lines with a passivation coating and including non-reflective nanoparticles in the patterning photoresist. The photoresist is mixed with catalytic nanoparticles wherein the nanoparticles are formed to minimize light reflection. The nanoparticles may be carbon coated metallic particles, or uncoated palladium nanoparticles. Also, a standoff photoresist layer may be included between the substrate and the photoresist composition to prevent reflection from the edges of the metallic lines.

The present disclosure relates to the method of manufacturing circuit having lamination layer using LDS (Laser Direct Structuring) to ease the application on surface structure for applied product of various electronic circuit and particularly, in which can form circuit structure of single-layer to multiple-layer on the surface of injection-molded substrate in the shape of plane or curved surface, metal product, glasses, ceramic, rubber or other material.

Embodiments may include inductors with embedded magnetic cores and methods of making such inductors. In an embodiment, an integrated circuit package may include an integrated circuit die with a multi-phase voltage regulator electrically coupled to the integrated circuit die. In such embodiments, the multi-phase voltage regulator may include a substrate core and a plurality of inductors. The inductors may include a conductive through-hole disposed through the substrate core and a plugging layer comprising a dielectric material surrounding the conductive through-hole. In an embodiment, a magnetic sheath is formed around the plugging layer. In an embodiment, the magnetic sheath is separated from the plated through hole by the plugging layer. Additionally, a first layer comprising a dielectric material may be disposed over a first surface of the magnetic sheath, and a second layer comprising a dielectric material may be disposed over a second surface of the magnetic sheath.

A component carrier and a method for manufacturing the same are disclosed. The component carrier includes an electrically conductive layer structure and an overhanging end. A first surface finish is formed on a first surface portion of the electrically conductive layer structure. Furthermore, the component carrier further includes a second surface finish on a second surface portion of the electrically conductive layer structure connected to the first surface finish and extending under the overhanging end.

A wiring circuit board includes a support metal layer having thermal conductivity of 5 W/m.Math.K or more, an insulating layer disposed on at least one side in a thickness direction of the support metal layer, a wiring layer disposed on a front surface of the insulating layer, a protective metal film disposed on the entire surface of the support metal layer between the support metal layer and the insulating layer, and a protective thin film disposed on an exposed surface exposed from the protective metal film in the support metal layer.