A base material for a printed circuit board includes: an insulating base film; a sintered layer that is layered on at least one side surface of the base film and that is formed of a plurality of sintered metal particles; an electroless plating layer that is layered on a surface of the sintered layer that is opposite to the base film; and an electroplating layer that is layered on a surface of the electroless plating layer that is opposite to the sintered layer, wherein an arithmetic mean height Sa of the surface of the electroless plating layer opposite to the sintered layer is greater than or equal to 0.001 m and less than or equal to 0.5 m.

There is provided a copper foil with a carrier particularly suitable for a circuit forming process for removing a carrier after laser drilling and desmear treatment, in detail, a copper foil with a carrier having high heat press resistance (heat resistance) of the carrier, laser drilling performance, corrosion resistance of the carrier against the desmear treatment, corrosion resistance of a release layer against the desmear treatment, and carrier release strength. The copper foil with a carrier comprises a carrier comprising at least one resin selected from polyethylene naphthalate (PEN) resins, polyethersulfone (PES) resins, polyimide resins, and polyphenylene sulfide resins; a silicon layer provided on the carrier, the silicon layer mainly containing silicon; a carbon layer provided on the silicon layer, the carbon layer mainly containing carbon; and an extremely thin copper layer provided on the carbon layer.

A method for making a circuit board uses a dielectric core, and at least one thin foil bottom surface with a foil backing of sufficient thickness to absorb heat from a laser drilling operation to prevent the penetration of the thin foil bottom surface during laser drilling. A sequence of steps including a laser drilling step, removing the foil backing step, electroless plating step, patterned resist step, electroplating step, resist strip step, tin plate step, and copper etch step are performed, which provide dot vias of fine linewidth and resolution.

Graphene oxide is used as an insulation barrier layer for metal deposition. After patterning and modification, the chemical characteristics of graphene oxide are induced. It can be used as the catalyst for electroless plating in the metallization process, so that the metal is only deposited on the patterned area. It provides the advantages of improving reliability and yield. The metallization structure includes a substrate, a graphene oxide catalytic layer, and a metal layer. It may be widely applied to the metallization of the fine pitch metal of a semiconductor package as well as the fine pitch wires of a printed circuit board (PCB), touch panels, displays, fine electrodes of solar cells, and so on.

Graphene oxide is used as an insulation barrier layer for metal deposition. After patterning and modification, the chemical characteristics of graphene oxide are induced. It can be used as the catalyst for electroless plating in the metallization process, so that the metal is only deposited on the patterned area. It provides the advantages of improving reliability and yield. The metallization structure includes a substrate, a graphene oxide catalytic layer, and a metal layer. It may be widely applied to the metallization of the fine pitch metal of a semiconductor package as well as the fine pitch wires of a printed circuit board (PCB), touch panels, displays, fine electrodes of solar cells, and so on.

According to one aspect of the present invention, a printed circuit board includes: an insulating base film; a conductive pattern that is partially layered on a surface side of the base film; a coating layer that is layered on a surface of a layered structure including the base film and the conductive pattern and having an opening portion that partially exposes the conductive pattern; and a tin plating layer that is layered on a surface of the conductive pattern exposed from the opening portion, wherein an average peel length of the coating layer from the conductive pattern with an inner edge of the opening portion as a base end is less than or equal to 20 m.

A method for selective metallization includes: selectively adsorbing catalytic nanoparticles onto an imprint mold to form a selectively adsorbed catalytic nanoparticle (SACN) mold; using the SACN mold in an imprinting process to synchronously transfer a pattern and the catalytic nanoparticles onto a film; separating the film from the SACN mold; and selectively depositing metal onto the film based on the pattern transferred to the film.

A conductive member includes a conductive fabric containing warp and weft as well as a support, includes at least one linear bend, and is imparted with electrical conductivity across the linear bend. In the conductive member, an angle formed between the linear bend and one of the warp and the weft is 5 to 45 C. The conductive fabric is preferably a conductive fabric obtained by layering a metal coating, formed by a wet plating method, on a fabric including a synthetic fiber.

A method for manufacturing a printed circuit board (PCB) with high component density includes at least two reinforcing plates, at least two connecting plates, a first circuit board unit, and a second circuit board unit. The reinforcing plate includes a supporting portion, a first connecting portion, and a second connecting portion. The first connecting portion and the second connecting portion connect to ends of the supporting portion. The connecting plates are bendable circuit boards. Each connecting plate is attached to the supporting portion, the first connecting portion, and the second connecting portion of a reinforcing plate. The first circuit board unit is fixed and electrically connected to a connecting plate away from first connecting portion. The second circuit board unit is fixed and electrically connected to a connecting plate away from the second connecting portion.

Embodiments include package substrates and a method of forming the package substrates. A package substrate includes a self-assembled monolayer (SAM) layer over a first dielectric, where the SAM layer includes first end groups and second end groups. The second end groups may include a plurality of hydrophobic moieties. The package substrate also includes a conductive pad on the first dielectric, where the conductive pad has a bottom surface, a top surface, and a sidewall, and where the SAM layer surrounds and contacts a surface of the sidewall of the conductive pad. The hydrophobic moieties may include fluorinated moieties. The conductive pad includes a copper material, where the top surface of the conductive pad has a surface roughness that is approximately equal to a surface roughness of the as-plated copper material. The SAM layer may have a thickness that is approximately 0.1 nm to 20 nm.