A printed circuit board has a core made of an aluminum material; a bonding member positioned on opposite surfaces of the core; a base layer bonded to the opposite surface of the core through the bonding member; a receiving hole extending through the core, the bonding member, and the base layer; a zinc substitution layer positioned on a surface of the base layer and a portion of the base layer exposed on an inner surface of the receiving hole; and a plating layer positioned on the zinc substitution layer, and having a circuit pattern.

Methods of forming microelectronic package structures are described. Those methods/structures may include forming a high density region on a board comprising a first plurality of conductive structures disposed on a dielectric material on the board, wherein the first plurality of conductive structures comprises a first pitch between individual ones of the first plurality of conductive structures. A low density region on the board comprises a second plurality of conductive structures disposed on the dielectric material, wherein the second plurality of conductive structures comprises a second pitch between individual ones of the second plurality of conductive structures, wherein the second pitch is more than about twice the magnitude of the first pitch.

A plating apparatus can perform a plating process on an entire surface of a substrate uniformly. A plating apparatus 20 includes a substrate holding/rotating device 110 configured to hold and rotate a substrate 2; a discharging device 21 configured to discharge a plating liquid toward the substrate 2 held on the substrate holding/rotating device 110; and a controller 160 configured to control the substrate holding/rotating device 110 and the discharging device 21. Further, the discharging device 21 includes a first nozzle 40 having a multiple number of discharge openings 41 arranged in a radial direction of the substrate 2 or having a discharge opening 42 extended in the radial direction of the substrate 2; and a second nozzle 45 having a discharge opening 46 configured to be positioned closer to a central portion of the substrate 2 than the discharge opening of the first nozzle 40.

[Problem to be Solved]

A multilayer flexible printed circuit board having a strip line advantageous to folding is provided.

[Solution]

A multilayer flexible printed circuit board 100 of an embodiment is a multilayer flexible printed circuit board having a strip line foldable at a folding part F1, the board including: a flexible insulative substrate 30; an inner layer circuit pattern 5 provided inside the flexible insulative substrate 30 and including a signal line 6 extending in a predetermined direction; a ground thin film 14a constituting a ground layer at least in the folding part F1 out of a ground layer of the strip line and constituted of a nonelectrolytic plating coat 14 formed on the flexible insulative substrate 30; and a protective layer 20 that covers the ground thin film 14a and is in close contact with an exposed part 19 from which the flexible insulative substrate 30 is exposed.

A method for manufacturing a printed wiring board includes forming the outermost conductor layer on the outermost resin insulating layer, forming a solder resist layer on the outermost resin insulating layer such that the solder resist layer covers the outermost conductor layer formed on the outermost resin insulating layer, irradiating plasma upon an exposed surface of the solder resist layer formed on the outermost conductor layer, forming a catalyst on the exposed surface of the solder resist layer formed on the outermost conductor layer, and forming an electroless plating layer on the exposed surface of the solder resist layer via the catalyst formed on the exposed surface of the solder resist layer such that the electroless plating layer has a film thickness in a range of 0.22 μm to 0.38 μm.

Embodiments may include inductors with embedded magnetic cores and methods of making such inductors. In an embodiment, an integrated circuit package may include an integrated circuit die with a multi-phase voltage regulator electrically coupled to the integrated circuit die. In such embodiments, the multi-phase voltage regulator may include a substrate core and a plurality of inductors. The inductors may include a conductive through-hole disposed through the substrate core and a plugging layer comprising a dielectric material surrounding the conductive through-hole. In an embodiment, a magnetic sheath is formed around the plugging layer. In an embodiment, the magnetic sheath is separated from the plated through hole by the plugging layer. Additionally, a first layer comprising a dielectric material may be disposed over a first surface of the magnetic sheath, and a second layer comprising a dielectric material may be disposed over a second surface of the magnetic sheath.

An electroless surface treatment plated layer of a printed circuit board, a method for preparing the same, and printed circuit board including the same. The electroless surface treatment plated layer includes: electroless nickel (Ni) plated coating/palladium (Pd) plated coating/gold (Au) plated coating, wherein the electroless nickel, palladium, and gold plated coatings have thicknesses of 0.02 to 1 μm, 0.01 to 0.3 μm, and 0.01 to 0.5 μm, respectively. In the electroless surface treatment plated layer of the printed circuit board, a thickness of the nickel plated coating is specially minimized to 0.02 to 1 μm, thereby making it possible to form an optimized electroless Ni/Pd/Au surface treatment plated layer.

The present invention relates to a composition for forming a conductive pattern and a resin structure having a conductive pattern, wherein the composition makes it possible to form a fine conducive pattern on various polymer resin products or resin layers through a simple process, and can more effectively meet needs of the art, such as displaying various colors.

Direct current plating methods inhibit void formation, reduce dimples and eliminate nodules. The method involves electroplating copper at a high current density followed by a pause in electroplating and then turning on the current to electroplate at a lower current density to fill through-holes.

A ceramic circuit substrate is suitable for silver nanoparticle bonding of semiconductor elements and has excellent close adhesiveness with a power module sealing resin. A ceramic circuit substrate has a copper plate bonded, by a braze material, to both main surfaces of a ceramic substrate including aluminum nitride or silicon nitride, the copper plate of at least one of the main surfaces being subjected to silver plating, wherein: the copper plate side surfaces are not subjected to silver plating; the thickness of the silver plating is 0.1 μm to 1.5 μm; and the arithmetic mean roughness Ra of the surface roughness of the circuit substrate after silver plating is 0.1 μm to 1.5 μm.