A wiring board includes a substrate, a wiring pattern area arranged on the substrate and including pieces of wiring, and a plurality of dummy pattern areas arranged around the wiring pattern area and electrically independent of the wiring. An aperture ratio of a first dummy pattern area, which is located next to the wiring pattern area, is not lower than an aperture ratio of the wiring pattern area. In addition, an aperture ratio of a second dummy pattern area, which is located next to the first dummy pattern area and farther from the wiring pattern area than the first dummy pattern area is, is higher than the aperture ratio of the first dummy pattern area.

A printed wiring board includes a first conductor layer, a resin insulating layer formed on the first conductor layer, a second conductor layer formed on a surface of the insulating layer, and a via conductor formed in an opening formed in the insulating layer such that the via conductor is connecting the first and second conductor layers. The second conductor layer and via conductor include a seed layer and an electrolytic plating layer formed on the seed layer such that the seed layer has a first portion formed on the surface of the insulating layer, a second portion formed on an inner wall surface of the insulating layer in the opening, and a third portion formed on the first conductor layer exposed from the opening and that the first portion has a thickness that is greater than a thickness of the second portion and a thickness of the third portion.

A wiring substrate includes a core substrate including a core insulating layer, a first conductor layer, a second conductor layer, a first insulating layer, a second insulating layer, a third conductor layer, and a fourth conductor layer. The first conductor layer includes first land and first plane parts, the second conductor layer includes second land and second plane parts, the third conductor layer includes fine wirings and a third plane part, the fourth conductor layer includes fine wirings and a fourth plane part, the substrate includes a through-hole conductor connecting the first and second land parts through the core insulating layer, a first via conductor connecting the first land part and third conductor layer, a second via conductor connecting the second land part and fourth conductor layer, a third via conductor connecting the first and third plane parts, and a fourth via conductor connecting the second and fourth plane parts.

A micronozzle assembly, comprising a reservoir, an array of structures comprising micronozzles, a porous structure positioned between the reservoir and the array, and an electrode within the reservoir, wherein the electrode comprises any of a mesh, a frame along the perimeter of the cavity of the reservoir, or a rod extending into a cavity of the reservoir.

Provided are: a surface-treated copper foil including a surface-treated layer formed on at least one side of an untreated copper foil and an oxidation preventing layer formed on the surface-treated layer, wherein the surface-treated layer contains copper particles having an average particle diameter of about 10 nm to about 100 nm and has a 10-point average roughness, Rz, of about 0.2 μm to about 0.5 μm and a gloss (Gs 60°) of about 200 or more, and the oxidation preventing layer contains nickel (Ni) and phosphorus (P); a manufacturing method thereof; a copper foil laminate including the same; and a printed wiring board including the same.

A method for manufacturing a multi-layer circuit board including an extreme fine via according to an embodiment of the disclosure may include: providing a board having one surface on at least a part of which an upper conductive layer is formed and the other surface on at least a part of which a lower conductive layer is formed; forming a lower metal layer on the other surface of the board; forming a first resist layer on the one surface of the board through a photolithography process, and forming a first opening on the first resist layer; forming a metal pillar by plating the first opening by using an electrolytic plating method; removing the first resist layer; forming an insulating layer on a location from which the first resist layer is removed; and evenly polishing the metal pillar and the insulating layer.

A multilayer substrate includes an element assembly including a second insulating layer and a first insulating layer arranged in this order from a first side to a second side with respect to a layer stacking direction, a first conductor layer on the first side of the first insulating layer and including a plated layer, and a second conductor layer on the first side of the second insulating layer. The first conductor layer includes a first connection portion and a first circuit portion, and the second conductor layer includes a second connection portion and a second circuit portion. When viewed from the layer stacking direction, the first circuit portion includes an overlapping portion which overlaps the second circuit portion. A portion of the first connection portion connected to the second connection portion has a maximum thickness greater than a maximum thickness of the overlapping portion.

A wiring board includes: a substrate having transparency; a plurality of first wirings which are arranged on an upper surface of the substrate and extend in a first direction and each of which has a back surface in contact with the substrate and a front surface facing an opposite side of the back surface; and has a back surface in contact with the substrate and a front surface facing an opposite side of the back surface. The first wiring has a pair of side surfaces which extend in the first direction and are adjacent to the back surface of the first wiring, and each of the pair of side surfaces of the second wiring is recessed inward. The second wiring has a pair of side surfaces which extend in the second direction and are adjacent to the back surface of the second wiring.

The present invention relates to methods and systems for deposition of metal conductors using asymmetrical electrolytic plating, in which one surface (e.g., top) of a substrate is coated with an electrical conductor, and an opposite (e.g., bottom, or other) surface of which is not coated. A channel is formed between the two sides of the substrate, passing through the substrate and, in some embodiments, passing through the conductor. Electrolytic plating is performed such that metal is deposited from the edge of the conduct proximal to the channel, along the side walls of the channel, and up to, and in some embodiments on to, the other side of the substrate. Use of etching or plate resist layers are also contemplated.

A method for forming a metal film includes forming an oxide layer on a to-be-treated surface of a to-be-treated object by bringing the to-be-treated surface into contact with a reaction solution containing fluorine and an oxide precursor, removing fluorine in the oxide layer, supporting a catalyst on the oxide layer by bringing the oxide layer into contact with a catalyst solution, and depositing a metal film on the oxide layer by bringing the oxide layer into contact with an electroless plating liquid.