Provided is a liquid mixture for filling blind holes in copper foil, relating to the technical field of electroplating hole filling. The liquid mixture comprises copper sulfate pentahydrate 210-240 g/L, citric acid 40-50 g/L, tartaric acid 10-20 g/L, chloride ion 40-70 ppm, accelerator 0.5-2 g/L, leveling agent 5-15 g/L, inhibitor 5-10 g/L, and sulfonate ion liquid 50-180 g/L. The leveling agent comprises tetranitro blue tetrazolium blue and triazolyl acetyl hydrazide.

A circuit board includes a first outer wiring layer, a circuit substrate, and a second outer wiring layer stacked. The circuit substrate includes a first inner wiring layer, an insulating layer, and a second inner wiring layer stacked. A plurality of thermally conductive pillars is arranged at intervals on the first inner wiring layer, a liquid storage space is formed between every two adjacent thermally conductive pillars, and a thermally conductive agent is received in the liquid storage space. The first outer wiring layer is formed on the plurality of thermally conductive pillars. The second outer wiring layer is formed the second inner wiring layer. A first groove penetrates the second outer wiring layer, the second inner wiring layer and the insulating layer, exposes a portion of the first inner wiring layer, and corresponds to the thermally conductive pillars. At least one heating element is installed in the first groove.

A component carrier includes an electrically insulating layer structure having a first main surface and a second main surface with a through hole extending through the electrically insulating layer structure between the first main surface and the second main surface. An electrically conductive bridge structure connects opposing sidewalls of the electrically insulating layer structure delimiting the through hole. A vertical thickness of the electrically insulating layer structure is not more than 200 μm and a narrowest vertical thickness of the bridge structure is at least 20 μm.

A circuit board with improved heat dissipation function and a method for manufacturing the circuit board are provided. The circuit board includes a heat dissipation substrate, an insulating layer on the heat dissipation substrate, an electronic component, a base layer on the insulating layer, and a circuit layer on the base layer. The heat dissipation substrate includes a phase change structure and a heat conductive layer wrapping the phase change structure. The heat dissipation substrate defines a first through hole. The insulating layer defines a groove for receiving the electronic component. A second through hole is defined in the circuit layer, the base layer, and the insulating layer. A bottom of the second through hole corresponds to the heat conductive layer. A heat conductive portion is disposed in the second through hole.

A method for forming a circuit board having a dielectric core, a foil top surface, and a thin foil bottom surface with a removable foil backing of sufficient thickness to absorb heat from a laser drilling operation to prevent the penetration of the thin foil bottom surface during laser drilling utilizes a sequence of steps including a laser drilling step, removing the foil backing step, electroless plating step, patterned resist step, electroplating step, resist strip step, tin plate step, and copper etch step, which provide dot vias of fine linewidth and resolution.

A component package includes a printed circuit board; a first electronic component disposed in a first region on the printed circuit board; a second electronic component disposed in a second region on the printed circuit board; and a metal wall disposed on the printed circuit board and spatially partitioning the first region and the second region on a plane. The metal wall is directly connected to the printed circuit board.

The present invention includes a method of fabricating an integrated RF power condition capacitor with a capacitance greater than or equal to 1 nf and less than 1 mm.sup.2, and a device made by the method.

A component carrier includes a stack with at least one electrically conductive layer structure, at least one electrically insulating layer structure, and a hole in the stack having a first hole portion covered with metal and having a second hole portion not covered with metal, wherein the second hole portion is defined by an anti-plating dielectric structure and an electroless plateable separation barrier.

A method for manufacturing a wiring substrate includes preparing a substrate including an insulating layer and metal foils, forming a through hole in the substrate to penetrate through the insulating layer and foils, forming a first plating film on the substrate such that the first film is formed on the entire surface of each metal foil and the inner wall of the hole, laminating one or more resin sheets on the first film such that the resin sheet or sheets cover the first film on the entire surface of a respective one of the foils, pressing the resin sheet or sheets such that resin is extruded from the resin sheet or sheets into the hole and fills space surrounded by the first film inside the hole, removing the resin sheet or sheets, and forming a second plating film on the substrate to cover surface of the resin in the hole.

A wiring substrate includes an insulating layer, and a build-up part formed on the insulating layer and including an interlayer insulating layer and a conductor layer. The build-up part has a cavity penetrating through the build-up part such that the cavity is formed to accommodate an electronic component and has an inner wall and a bottom surface having a groove and that the groove is extending entirely in an outer edge part of the bottom surface and formed continuously from the inner wall surface of the cavity.