A component package includes a printed circuit board; a first electronic component disposed in a first region on the printed circuit board; a second electronic component disposed in a second region on the printed circuit board; and a metal wall disposed on the printed circuit board and spatially partitioning the first region and the second region on a plane. The metal wall is directly connected to the printed circuit board.

A method for manufacturing a circuit board with narrow conductive traces and narrow spaces between traces includes a base layer and two first wiring layers disposed on opposite surfaces of the base layer. Each first wiring layer includes a first bottom wiring and a first electroplated copper wiring. The first bottom wiring is formed on the base layer. The first bottom wiring includes a first end facing the base layer, a second end opposite to the first end, and a first sidewall connecting the first end and the second end. The first electroplated copper wiring covers the second end and the first sidewall of the first bottom wiring.

A method for manufacturing a printed wiring board includes forming the outermost conductor layer on the outermost resin insulating layer, forming a solder resist layer on the outermost resin insulating layer such that the solder resist layer covers the outermost conductor layer formed on the outermost resin insulating layer, irradiating plasma upon an exposed surface of the solder resist layer formed on the outermost conductor layer, forming a catalyst on the exposed surface of the solder resist layer formed on the outermost conductor layer, and forming an electroless plating layer on the exposed surface of the solder resist layer via the catalyst formed on the exposed surface of the solder resist layer such that the electroless plating layer has a film thickness in a range of 0.22 μm to 0.38 μm.

Direct current plating methods inhibit void formation, reduce dimples and eliminate nodules. The method involves electroplating copper at a high current density followed by electroplating at a lower current density to fill through-holes.

A FPC board and a method for manufacturing the same and an OLED display device are provided. The FPC board includes a substrate, a first wire layer disposed on one side of the substrate, a circuit board terminal disposed at an edge on one side of the substrate and connected to the first wire layer, and a first protective layer covering the first wire layer. The thickness of the circuit board terminal is larger than the sum of the thicknesses of the first wire layer and the first protective layer. When the FPC board is connected to the OLED panel, one side of the base substrate on which the panel terminal is provided is opposite to one side of the substrate on which the circuit board terminal is provided, such that the base substrate overlaps with the substrate to connect the circuit board terminal and the panel terminal.

An aqueous electrolytic composition and a process for electrodeposition of copper on a dielectric or semiconductor base structure using the aqueous electrolytic composition. The process includes (i) contacting a metalizing substrate comprising a seminal conductive layer on the base structure with an aqueous electrolytic deposition composition; and (ii) supplying electrical current to the electrolytic deposition composition to deposit copper on the substrate. The aqueous electrolytic composition comprises: (a) copper ions; (b) an acid; (c) a suppressor; and (d) a quaternized poly(epihalohydrin) comprising n repeating units corresponding to structure 1N and p repeating units corresponding to structure 1P:

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A wiring board (10) includes a substrate (11) that is transparent and a wiring pattern region (20) that is disposed on the substrate (11) and that includes a plurality of wiring lines (21, 22). The wiring pattern region (20) has a sheet resistance of less than or equal to 5 Ω/sq, and each wiring line (21, 22) has a maximum width of less than or equal to 3 μm when viewed at a viewing angle of 120°.

A wiring board includes an insulating base including a first principal surface, a second principal surface opposite to the first principal surface, and a first through hole penetrating the insulating base from the first principal surface to the second principal surface, a functional material provided inside the first through hole, a first insulating layer covering the first principal surface, and a first surface of the functional material, and a second insulating layer covering the second principal surface, and a second surface of functional material. A second through hole is formed in the first insulating layer, the functional material, and the second insulating layer, and a conductive layer is formed on a wall surface of the second through hole.

The disclosure relates to a method for manufacturing a transfer film including an electrode layer, the method comprising: an electrode layer formation step of forming an electrode layer on a carrier member by using a conductive material; a placement step of placing the carrier member on at least one side of an insulating resin layer respectively; a bonding step of bonding the carrier member and the insulating resin layer together by applying pressure thereto; and a transfer step of removing the carrier member to transfer the electrode layer on the insulating resin layer.

First, a patterned substrate including an insulating substrate, a conductive seed layer, and an insulating layer is prepared. The seed layer is disposed on the insulating substrate, and consists of a first part having a predetermined pattern corresponding to the wiring pattern and a second part as a part other than the first part. The insulating layer is disposed on the second part of the seed layer. Subsequently, a metal layer having a thickness larger than a thickness of the insulating layer is formed on the first part of the seed layer. Here, a voltage is applied between an anode and the seed layer while a resin film containing a metal ion-containing solution is disposed between the patterned substrate and the anode and the resin film and the seed layer are brought into pressure contact. Subsequently, the insulating layer and the second part of the seed layer are removed.