Patent classifications
H05K2203/1366
CONFORMAL COATING FOR ELECTRONIC DEVICES AND METHODS OF COATING
A method of forming an electronic circuit component comprises (a) depositing nanoparticle ink comprising conductive material on a substrate; (b) curing the nanoparticle ink to form cured nanoparticle ink; (c) subjecting the cured nanoparticle ink to a first precursor gas to form a first layer of precursor material on the cured nanoparticle ink; and (d) subjecting the first layer of precursor material to a second precursor gas so that the first layer of precursor material reacts with the second precursor gas to form an oxide layer on the cured nanoparticle ink.
AQUEOUS BASED NANOPARTICLE INK
Water-based nanoparticle inks may be formulated to be compatible with printed electronic direct-write methods. The water-based nanoparticle inks may include a functional material (nanoparticle) in combination with an appropriate solvent system. A method may include dispersing nanoparticles in a solvent and printing a circuit in an aerosol jet process or plasma jet process.
METHOD FOR REPAIRING COATED PRINTED CIRCUIT BOARDS
A method for repairing a printed circuit board (PCB) including the steps of presenting a PCB having an initial coating on a surface thereof, removing the initial coating from the surface of the PCB at least in an area in need of repair, and recoating at least the area of the PCB in need of repair by way of atomic layer deposition.
INTERPOSER WITH MANGANESE OXIDE ADHESION LAYER
A method of forming an article, comprising: forming an adhesion layer comprising MnO.sub.x on a glass, glass-ceramic or ceramic wafer; calcining the adhesion layer such that a first portion of the MnO.sub.x of the adhesion layer is chemically bonded to the wafer; depositing a metal layer on the adhesion layer; and processing the metal layer and the adhesion layer such that a portion of the MnO.sub.x of the adhesion layer is chemically bonded to the metal layer.
METHOD FOR FORMING CIRCUIT PATTERN ON SURFACE OF THREE-DIMENSIONAL STRUCTURE
A method for forming a circuit pattern on a surface of a 3D structure includes: forming a first insulation layer on the surface of the 3D structure; forming a conductive pattern on the first insulation layer; forming a second insulation layer on the conductive pattern except for a circuit element mounting region; and mounting one or more circuit elements on the circuit element mounting region.
Processing machine
A processing machine can include motors; at least one heater; first and second processing enclosures separated by a gap; an upper level conveyor that passes circuit assemblies through the first and second processing enclosures and the gap; a lower level conveyor that passes the circuit assemblies through the first and second processing enclosures and the gap; an elevator that transports the circuit assemblies between the upper level conveyor and the lower level conveyor; and a controller that includes circuitry operatively coupled to the motors and to the at least one heater.
ENCLOSURE WITH TAMPER RESPONDENT SENSOR
A method to fabricate a tamper respondent assembly is provided. The tamper respondent assembly includes an electronic component and an enclosure at least partly enclosing the electronic component. A piezoelectric sensor is integrated in the enclosure. The integrating includes providing a base structure that includes a first conductive layer, depositing a piezoelectric layer on the first conductive layer, covering the piezoelectric layer with a second conductive layer, and providing sensing circuitry for observing sensing signals of the piezoelectric layer. The piezoelectric layer includes a plurality of nanorods. Aspects of the invention further relates to a corresponding assembly and a corresponding computer program product.
DRAPABLE, FLEXIBLE CIRCUITRY LAYERS AND METHODS THEREFOR
A mechanical subtractive method of manufacturing a flexible circuitry layer may include mechanically removing at least a portion of a conductive mesh, wherein, following the mechanical removal, a remaining portion of the conductive mesh forms at least a portion of a circuitry trace comprising an electrode; forming an electrical connection between the electrode and a terminal of an interfacing component, wherein the interfacing component comprises a connector; and encasing at least a portion of the circuit trace with an insulative layer.
Method of conformal coating
A method of, and system for, providing an amorphous fluorinated polymer conformal coating to an RF circuit board is described. A coating solution including the amorphous fluorinated polymer dissolved in a fluorinated solvent is provided. The coating solution is applied to the RF circuit board via a mechanically controlled fluid spray application device to produce a coated board. A predetermined time period is waited for substantial evaporation of the fluorinated solvent from the coated board, thus leaving behind a conformal coating of the amorphous fluorinated polymer on a board surface area.
BI-LAYER PREPREG FOR REDUCED DIELECTRIC THICKNESS
An apparatus is provided which comprises: a woven fiber layer, a first resin layer on a first surface of the woven fiber layer, a second resin layer on a second surface of the woven fiber layer, the second surface opposite the first surface, and the first and the second resin layers comprising cured resin, a third resin layer on the first resin layer, and a fourth resin layer on the second resin layer, the third and the fourth resin layers comprising an uncured resin, and wherein the fourth resin layer has a thickness greater than a thickness of the third resin layer. Other embodiments are also disclosed and claimed.