A semiconductor device includes a semiconductor substrate, a capacitor structure, a first contact plug, and a spacer. The capacitor structure is over the semiconductor substrate. The capacitor structure includes a bottom electrode, a capacitor dielectric, and a top electrode. The bottom electrode is over the semiconductor substrate. The capacitor dielectric is over a first portion of the bottom electrode. The top electrode is over the capacitor dielectric. The first contact plug is over and electrically connected to a second portion of the bottom electrode. The spacer is adjacent at least a sidewall of the second portion of the bottom electrode.

A semiconductor device includes first bit lines disposed on a substrate. Buried contacts disposed among first bit lines and connected to the substrate are provided. Landing pads are disposed on the buried contacts. Second bit lines are disposed on a peripheral area of the substrate. Upper surfaces of the second bit lines and the landing pads are coplanar with each other. First insulating patterns are disposed among the second bit lines. Second insulating patterns are disposed among the landing pads. Cell capacitors connected to the landing pads are disposed. The first insulating patterns include an insulating layer different from at least one insulating layer of the second insulating patterns.

An apparatus includes a semiconductor substrate; an access transistor including channel, source and drain regions arranged in a vertical direction to the semiconductor substrate and a gate-electrode facing to the channel region; a storage capacitor coupled to one of the source and drain regions; a bit-line coupled to the other of the source and drain regions; and a pull-out-electrode connected to the bit-line; wherein surfaces of the source and drain regions and the pull-out-electrode on the bit-line side is arranged at substantially the same height from the upper surface of the semiconductor substrate.

A capacitor structure is provided, which includes a contact layer, an insulating layer, a bottom conductive plate, a dielectric layer and a top conductive plate. The contact layer has first, second, third, fourth and fifth portions arranged from periphery to center. The insulating layer is disposed over the contact layer and has an opening exposing the contact layer. The bottom conductive plate is disposed in the opening and including first, second and third portions extending along a depth direction of the opening and separated from each other and in contact with the first, third and fifth portions of the contact layer, respectively. The dielectric layer is conformally disposed on the bottom conductive plate and in contact with the second and fourth portions of the contact layer. The top conductive plate is disposed on the dielectric layer. A method of manufacturing the capacitor is also provided.

Examples herein relate to three-dimensional (3D) dynamic random access memory (DRAM) and corresponding methods. In an example, a film stack is formed on a substrate. The film stack includes multiple unit stacks, each having, sequentially, a first dielectric layer, a semiconductor layer, and a second dielectric layer. A first opening is formed through the film stack. The second dielectric layer is pulled back from the first opening forming a first lateral recess. A gate structure is formed in the first lateral recess and disposed on a portion of the semiconductor layer. A second opening, laterally disposed from where the first opening was formed, is formed through the film stack. The portion of the semiconductor layer is pulled back from the second opening forming a second lateral recess. A capacitor is formed in a region where the second lateral recess was disposed and contacting the portion of the semiconductor layer.

Semiconductor memory devices are provided. A semiconductor memory device includes a substrate. The semiconductor memory device includes a plurality of memory cell transistors vertically stacked on the substrate. The semiconductor memory device includes a first conductive line connected to a source region of at least one of the plurality of memory cell transistors. The semiconductor memory device includes a second conductive line connected to a plurality of gate electrodes of the plurality of memory cell transistors. Moreover, the semiconductor memory device includes a data storage element connected to a drain region of the at least one of the plurality of memory cell transistors.

Embodiments of the present disclosure provide a method and a device for determining a fabrication chamber. According to a current radio frequency power time of each of the fabrication chambers corresponding to adjacent process steps and service phases divided based on a service period of the fabrication chambers, a service phase is determined for the current radio frequency power time of each of the fabrication chambers. For target objects processed by the fabrication chambers in the current process step, fabrication chambers for the target objects to enter in a next process step are directly determined according to the service phase of the current radio frequency power time of each of the fabrication chambers.

Embodiments relate to a semiconductor structure and a method for fabricating the same. The method includes: providing a substrate; forming a first isolation trench in the substrate; filling a first isolation dielectric layer in the first isolation trench; forming a second isolation trench; forming a second isolation dielectric layer in the second isolation trench; forming word line structures arranged at intervals, where the word line structures extend along the second direction to wrap the channel regions of the active pillars in a same row; etching back the second isolation dielectric layer and the first isolation dielectric layer to expose second connection terminals of the active pillars; and forming a protective layer configured to define positions of the word line structures and wrap the second connection terminals of the active pillars.

A semiconductor memory device comprises: a laterally oriented hybrid channel including outer channel materials and an inner channel material interposed between the outer channel materials; a laterally oriented double word line with the hybrid channel interposed therebetween; a vertically oriented bit line connected to a first end of the hybrid channel; and a capacitor connected to a second end of the hybrid channel.

An indirect heating method using a laser according to an aspect of the present disclosure includes: a first process of adjacently placing a first material structure containing metal and a second material structure containing inorganic material; and a second process of directly heating the first material structure to indirectly heat the second material structure adjacent to the first material structure by radiating a laser to the first material structure.