Methods of forming a three-dimensional dynamic random-access memory (3D DRAM) structure are provided herein. In some embodiments, a method of forming a 3D DRAM structure includes forming at least one wordline feature in a first stack comprising a plurality of crystalline silicon (c-Si) layers alternating with a plurality of crystalline silicon germanium (c-SiGe) layers, wherein the wordline feature comprises: vertically etching a first pattern of holes; filling the first pattern of holes with a silicon germanium fill; vertically etching a plurality of isolation slots through the first stack; filling the plurality of isolation slots with a dielectric material to form an isolation layer between the silicon germanium fill; etching the silicon germanium fill and the plurality of c-SiGe layers to form a plurality of gate silicon channels comprising portions of the plurality of c-Si layers; and depositing a layer of conductive material that wraps around the plurality of gate silicon channels.

A memory structure includes a spacer between a first side of a wordline conductor and a bitline conductor. A semiconductor material has horizontal portions extending from the bitline conductor along a top and bottom of the wordline conductor and has a contact portion extending along a second side of the wordline conductor between and connecting the horizontal portions. A high-κ dielectric is between the semiconductor material and the wordline conductor. A capacitor has a first conductor, a second conductor, and an insulator between the first and second conductors, where the first conductor contacts the contact portion of the semiconductor material along the first side of the wordline conductor, and the second conductor connects to a ground terminal.

A semiconductor memory device includes a stack structure including word lines and interlayer dielectric patterns that are alternately and repeatedly stacked on a semiconductor substrate. Semiconductor patterns are respectively disposed between vertically adjacent word lines. A bit line vertically extends from the semiconductor substrate and contacts the semiconductor patterns. A capping insulating pattern is disposed between the bit line and the word lines and covers side surfaces of the interlayer dielectric patterns. Memory elements are respectively disposed between vertically adjacent interlayer dielectric patterns. Each of the semiconductor patterns comprises a first source/drain region that contacts the bit line, a second source/drain region that directly contacts one memory element of the memory elements, and a channel region between the first and second source/drain regions. A largest width of the first source/drain region is greater than a width of the channel region.

A method includes forming a stack of material layers to cover an array region and a periphery region of a substrate. A first patterned mask layer is formed, and the pattern of the first patterned mask layer is transferred to the stack of material layers, thereby forming a first array pattern and a first periphery pattern respectively in the array and periphery regions. A second patterned mask layer is provided above the first array and periphery patterns. The pattern of the second patterned mask is not aligned with the pattern of the first patterned mask. The pattern of the second patterned mask layer is transferred to form the first and second sacrificial patterns respectively in the array and periphery regions. The first array pattern, the first and second sacrificial patterns, and the first periphery pattern are simultaneously transferred to form a second array pattern and a second periphery pattern.

Systems, methods and apparatus are provided for an array of vertically stacked memory cells having horizontally oriented access devices and access lines, and shared vertically oriented digit line. The access devices having a first source/drain region and a second source drain region separated by a channel region, and gates opposing the channel region. Horizontal oriented access lines are coupled to the gates and separated from a channel region by a gate dielectric. The memory cells have horizontally oriented storage nodes coupled to the second source/drain region of the horizontally oriented access devices. The shared, vertically oriented digit line is shared between two neighboring horizontal access devices and is coupled to the first source/drain regions of the two neighboring horizontally oriented access devices.

A semiconductor device includes: a substrate, and a plurality of conductors. A plurality of conductors are configured to form first electrodes of capacitor structures, and are distributed on one side of the substrate in rows and columns. Each of the conductors comprises a columnar body and a plurality of annular bumps. A part of an axial direction of the columnar body is intersected with the substrate. The annular bumps are arranged around the circumference of the columnar body, and a protruding direction of the annular bumps is parallel to the substrate. The plurality of annular bumps are distributed at intervals in the axial direction of the columnar body. Annular bumps of the conductors adjacent in row and column directions are staggered in a direction perpendicular to the substrate.

Present invention relates to a highly-integrated memory cell and a semiconductor device including the same. According to an embodiment of the present invention, a semiconductor device comprises: an active layer including a channel, the active layer being spaced apart from a substrate and extending in a direction parallel to a surface of the substrate; a gate dielectric layer formed over the active layer; a word line laterally oriented in a direction crossing the active layer over the gate dielectric layer and including a low work function electrode and a high work function electrode, the high work function electrode having a higher work function than the low work function electrode; and a dipole inducing layer disposed between the high work function electrode and the gate dielectric layer.

A semiconductor device includes a substrate, a plurality of bit lines, a plurality of contacts, a plurality of storage node pads, a capacitor structure and a plurality of first interface layers. The bit lines and the contacts are disposed on the substrate, and the contacts are alternately and separately disposed with the bit lines. The storage node pads are disposed on the contacts and the bit lines, and are respectively aligned with the contacts. The capacitor structure is disposed on the storage node pads. The first interface layers are disposed between the storage node pads and the capacitor structure, and the first interface layers include a metal nitride material. The first interface layers may improve the granular size of the storage node pads, and reduce the surface roughness thereof, and further improve the electrical connection between the storage nodes and transistor components below.

Provided is a capacitor device, a unit synapse using the capacitor device, a synapse array using the unit synapses. The capacitor device comprises a semiconductor layer which include first and second doping regions formed to be spaced apart from each other and a body region formed between the first and second doping regions; a gate electrode provided above the body region; and a gate insulator stack to have a memory function and disposed between the gate electrode and the semiconductor layer. The capacitance between the gate electrode and the first doping region is determined according to information stored in the gate insulator stack, and the state of the capacitor device is determined according to the capacitance to be one of two preset states. The unit synapse comprises a pair of capacitor devices to perform an XNOR operation.

Semiconductor memory devices and methods of forming the same are provided. The semiconductor devices may include a vertical insulating structure extending in a first direction on a substrate, a semiconductor pattern extending along a sidewall of the vertical insulating structure, a bitline on a first side of the semiconductor pattern, an information storage element on a second side of the semiconductor pattern and including first and second electrodes, and a gate electrode on the semiconductor pattern and extending in a second direction that is different from the first direction. The bitline may extend in the first direction and may be electrically connected to the semiconductor pattern. The first electrode may have a cylindrical shape that extends in the first direction, and the second electrode may extend along a sidewall of the first electrode.