An embodiment provides a method for fabricating a semiconductor structure. The method includes: providing a semiconductor substrate having an active area, the active area including a first active area and a second active area isolated from each other; forming a bitline contact groove on the semiconductor substrate, the bitline contact groove exposing the first active area; forming an etch stop layer covering a sidewall of the bitline contact groove, the etch stop layer exposing a partial area of the first active area at a bottom of the bitline contact groove; etching the semiconductor substrate by using the etch stop layer as a mask to form a pit at the bottom of the bitline contact groove, the pit being at least partially positioned in the first active area; removing the etch stop layer; forming a bitline structure; and forming a conductive plug electrically connected to the second active area.

Semiconductor devices are provided. A semiconductor device includes a substrate. The semiconductor device includes a stack structure on the substrate. The stack structure includes a first insulating material and a second insulating material that is on the first insulating material. The semiconductor device includes a spacer that extends from a sidewall of the first insulating material of the stack structure to a portion of a sidewall of the second insulating material of the stack structure. Moreover, the semiconductor device includes a conductive line that is on the spacer. Methods of forming semiconductor devices are also provided.

A DRAM including following components is provided. A bit line stack structure includes a bit line structure and a hard mask layer. The bit line structure is located on the substrate. The hard mask layer is located on the bit line structure. A dielectric layer is located on the bit line stack structure and has an opening. A contact structure is located on the substrate and includes an active region contact and a capacitor contact. The active region contact is located on the substrate. The top surface of the active region contact is exposed by the opening. The capacitor contact is located in the opening over the active region contact. An isolation layer is located between the hard mask layer and the dielectric layer and between the capacitor contact and the bit line stack structure. An etch stop layer is located between the dielectric layer and the isolation layer.

The present disclosure relates to a semiconductor structure and a manufacturing method thereof. The semiconductor structure includes: a substrate including a peripheral region, wherein the peripheral region includes a wire lead-out area, and the substrate is arranged with a plurality of discrete bit line structures; a dielectric layer formed between the adjacent bit line structures, wherein the peripheral region is arranged with a first contact hole; a wire lead-out area with a second through hole; a filling layer filling part of a first contact hole, wherein a remaining part of the first contact hole is defined as a first through hole; a first conductive layer located in the first through hole and the second through hole; and a conductive connecting wire located over the dielectric layer and being in contact with the first conductive layer in the wire lead-out area.

The present disclosure provides a method of manufacturing a semiconductor structure and a semiconductor structure. The method includes: providing a base; forming a plurality of support layers on the base, where the support layers are configured to support a plate capacitor structure, extend along a first direction, and are arranged at intervals along a second direction, and the first direction intersects the second direction; forming a bottom electrode layer, where the bottom electrode layer at least covers sidewalls of the support layers; and forming a dielectric layer, the dielectric layer covering the bottom electrode layer.

A semiconductor device and a related fabrication method are provided. The semiconductor device includes a conductive line on a substrate, a capping pattern that extends along an upper surface of the conductive line, a spacer structure that extends along a side surface of the conductive line and a side surface of the capping pattern, a buried contact electrically connected to the substrate, on a side surface of the spacer structure, a barrier conductive film extending along the buried contact and the spacer structure, and a landing pad electrically connected to the buried contact, on the barrier conductive film and the capping pattern, wherein an upper part of the spacer structure includes a spacer recess that is lower than or equal to an uppermost surface of the capping pattern, and the barrier conductive film extends along the spacer recess and does not cover the uppermost surface of the capping pattern.

A semiconductor device including a substrate, lower electrodes disposed on the substrate, at least one support layer in contact with the lower electrodes, a dielectric layer disposed on the lower electrodes, an upper electrode disposed on the dielectric layer, a first interfacial film between the lower electrodes and the dielectric layer, and a second interfacial film between the upper electrode and the dielectric layer. At least one of the first and second interfacial films includes a plurality of layers, wherein the plurality of layers include a first metal element, and a second metal element, and at least one of oxygen \and nitrogen. The lower electrodes include the first metal element. A first region of the first interfacial film includes the second metal element at a first concentration and a second region of the first interfacial film includes the second metal element at a second concentration different from the first concentration.

A semiconductor device includes a substrate including first and second active regions; a bitline structure extending in one direction on the substrate, the bitline structure being electrically connected to the first active region; a storage node contact on a sidewall of the bitline structure, the storage node contact being electrically connected to the second active region; a spacer structure between the bitline structure and the storage node contact; a landing pad on the storage node contact, the landing pad being in contact with a sidewall of the spacer structure; and a capacitor structure electrically connected to the landing pad, wherein the spacer structure includes a first spacer, a second spacer, a third spacer, and a fourth spacer, sequentially stacked on the sidewall of the bitline structure, the second spacer is an air spacer, and the third spacer has a thickness that is less than a thickness of the first spacer.

The present disclosure provides a method for manufacturing a semiconductor structure. The method includes forming a bit line on a substrate, forming a first dielectric layer over the substrate and surrounding a lower portion of the bit line, forming a second dielectric layer over the bit line and the first dielectric layer, forming a contact over the second dielectric layer, wherein a height of the contact above the substrate is greater than a height of the first dielectric layer above the substrate, removing the first dielectric layer and the second dielectric layer, and forming a third dielectric layer conformally over the bit line, the substrate and the contact, thereby forming an air gap between the contact and the bit line.

A semiconductor device includes a substrate including cell and core regions respectively having first and second active patterns having respective, opposing sidewall surfaces at least partially defining a trench therebetween, and a boundary region between the cell and core regions, a device isolation layer on the boundary region to fill the trench, a line structure on the first active pattern and extended from the cell region to the boundary region, and a capping pattern covering an end of the line structure on the boundary region. The device isolation layer includes one or more inner surfaces at least partially defining a recess region, which is adjacent to the end of the line structure, and the capping pattern is extended along the end of the line structure into the recess region. A top surface of the device isolation layer is between the line structure and a bottom surface of the capping pattern.