A memory cell includes a substrate, a deep trench (DT) capacitor formed in the substrate, at least an insulting layer formed on the substrate, and an oxide semiconductor field effect transistor (OS FET) device formed on the insulating layer. And more important, the OS FET device is electrically connected to the DT capacitor.

The present disclosure provides a method of manufacturing a semiconductor device. The method includes providing a substrate; forming a conductive layer on the substrate; patterning the conductive layer to form a first metallization layer and a second metallization layer extending along a first direction, wherein the first metallization layer has a first protruding portion protruding toward the second metallization layer; and forming a first channel layer within the first metallization layer and a second channel layer within the second metallization layer.

A deep trench (DT) opening is provided in a semiconductor substrate and then conducting carbon nanotubes are formed within the DT. Each conducting carbon nanotube is coated with a high k dielectric material and thereafter the remaining volume of the DT is filled with a conductive material.

Methods of forming polysilicon-filled deep trenches for an eDRAM are provided. The method may include forming a plurality of polysilicon-filled deep trenches in a substrate. An epitaxy-retarding dopant is introduced to an upper portion of the trenches. A plurality of fins are then formed over the substrate, with each polysilicon-filled deep trench including a corresponding fin extending thereover. A silicon layer is epitaxially grown over at least the polysilicon-filled deep trench. The dopant in the polysilicon-filled deep trenches acts to control the epitaxial growth of the silicon layer, diminishing or preventing shorts to adjacent fins and/or deep trenches at advanced technology nodes.

An integrated FinFET and deep trench capacitor structure and methods of manufacture are disclosed. The method includes forming at least one deep trench capacitor in a silicon on insulator (SOI) substrate. The method further includes simultaneously forming polysilicon fins from material of the at least one deep trench capacitor and SOI fins from the SOI substrate. The method further includes forming an insulator layer on the polysilicon fins. The method further includes forming gate structures over the SOI fins and the insulator layer on the polysilicon fins.

An integrated FinFET and deep trench capacitor structure and methods of manufacture are disclosed. The method includes forming at least one deep trench capacitor in a silicon on insulator (SOI) substrate. The method further includes simultaneously forming polysilicon fins from material of the at least one deep trench capacitor and SOI fins from the SOI substrate. The method further includes forming an insulator layer on the polysilicon fins. The method further includes forming gate structures over the SOI fins and the insulator layer on the polysilicon fins.

A semiconductor structure includes a replacement strap for a finFET fin that provides communication between a storage capacitor and the fin. The storage capacitor is located in a deep trench formed in a substrate and the fin is formed on a surface of the substrate. The replacement strap allows for electrical connection of the fin to the storage capacitor and is in direct physical communication with the fin and the storage capacitor. The replacement strap may be formed by removing a sacrificial strap and merging epitaxially grown material from the fin and epitaxially grown material from the capacitor. The epitaxially grown material grown from the fin grows at a slower rate relative to the epitaxially grown material grown from the capacitor. By removing the sacrificial strap prior to forming the replacement strap, epitaxial overgrowth that may cause shorts between adjacent capacitors is limited.

Provided are a thin film structure, a capacitor including the thin film structure, a semiconductor device including the thin film structure, and a method of manufacturing the thin film structure, in which the thin film structure may include: a first electrode thin film disposed on a substrate and including a first perovskite-based oxide; and a protective film disposed on the first electrode thin film and including a second perovskite-based oxide that is oxygen-deficient and includes a doping element. The thin film structure may prevent the deterioration of conductivity and a crystalline structure of a perovskite-based oxide electrode, which is a lower electrode, even in a high-temperature oxidizing atmosphere for subsequent dielectric film deposition.

Provided are a thin film structure, a capacitor including the thin film structure, a semiconductor device including the thin film structure, and a method of manufacturing the thin film structure, in which the thin film structure may include: a first electrode thin film disposed on a substrate and including a first perovskite-based oxide; and a protective film disposed on the first electrode thin film and including a second perovskite-based oxide that is oxygen-deficient and includes a doping element. The thin film structure may prevent the deterioration of conductivity and a crystalline structure of a perovskite-based oxide electrode, which is a lower electrode, even in a high-temperature oxidizing atmosphere for subsequent dielectric film deposition.

A semiconductor structure includes a substrate, and a plurality of first semiconductor columns, a storage structure, a plurality of transistors and a first protective layer located above the substrate. The plurality of first semiconductor columns are arranged in array in first and second directions. Each first semiconductor column includes a first part and a second part located on same. The second part includes a bottom portion, an intermediate portion and a top portion. The first direction and the second direction intersect with each other and are both parallel to top surface of the substrate. The storage structure surrounds sidewalls of the first parts. The first protective layer surrounds sidewalls of the top portions of the second parts. A channel structure of each transistor is located in the intermediate portion of the second part, and an extending direction of the channel structure is the same as that of the second part.