Systems, devices, and methods for managing three-dimensional (3D) semiconductor devices are provided. In one aspect, a semiconductor device includes an array structure having a plurality of memory cells. A memory cell of the plurality of memory cells includes a transistor and a capacitor that are stacked together. The transistor includes a transistor body, a first terminal, a second terminal, and a gate structure. The first terminal of the transistor is in contact with a first electrode of the capacitor along the first direction. The gate structure includes a conductive film having an angled or curved end closer to the first terminal of the transistor than the second terminal of the transistor.

A memory device include a bit line extending in a first direction, a first transistor comprising a first semiconductor body extending in a second direction perpendicular to the first direction and a first gate structure located at one side of the first semiconductor body in the first direction, the first semiconductor body coupled to the bit line, a second transistor comprising a second semiconductor body extending in the second direction and a second gate structure located at one side of the second semiconductor body in the first direction, the second semiconductor body coupled to the bit line; and a first isolation structure located between the first semiconductor body and the second semiconductor body in the first direction. The first semiconductor body is in contact with the first isolation structure, and the second semiconductor body is in contact with the first isolation structure

A semiconductor structure includes: a substrate, a first gate structure, and a second gate structure. The substrate includes: discrete first semiconductor pillars arranged at a top of the substrate and extending in a vertical direction; and a second semiconductor pillar and a third semiconductor pillar extending in the vertical direction, the second and third semiconductor pillars are provided at a top of each first semiconductor pillar. The first gate structure is arranged in a middle region of the first semiconductor pillar and surrounds the first semiconductor pillar. The second gate structure is arranged in a middle region of the second semiconductor pillar and of the third semiconductor pillar, and includes a first ring structure and a second ring structure. The first ring structure surrounds the second semiconductor pillar, and the second ring structure surrounds the third semiconductor pillar.

A semiconductor structure, a method for manufacturing a semiconductor structure, and a memory are provided. The semiconductor structure includes: a plurality of first semiconductor pillars, a plurality of second semiconductor pillars, a first support layer, and a storage structure. The plurality of first semiconductor pillars are arranged in an array in a first direction and in a second direction. Each of the first direction and the second direction is perpendicular to an extending direction of each first semiconductor pillar, and the first direction intersects with the second direction. The first support layer covers sidewalls of top portions of the plurality of first semiconductor pillars. Each second semiconductor pillar is arranged on a respective one of the plurality of first semiconductor pillars. The storage structure is arranged around at least sidewalls of the plurality of first semiconductor pillars and sidewalls of the plurality of second semiconductor pillars.

A semiconductor device according to an example embodiment of the present disclosure includes a memory cell array region including memory cells, each of the memory cells including a cell transistor and an information storage structure, and a peripheral circuit region spaced apart from the memory cell array region in a horizontal direction. The peripheral circuit region includes an upper interconnection on a first level, a lower interconnection on a second level that is spaced apart from the first level in a vertical direction that is perpendicular to the horizontal direction, and at least one peripheral transistor between the first level and the second level, where the at least one peripheral transistor includes a channel structure extending in the vertical direction.

A method of manufacturing a semiconductor device includes forming a stack structure including interlayer insulating layers and horizontal layers alternately stacked in a vertical direction; forming a first vertical structure and a second vertical structure spaced apart from each other, the first and second vertical structures penetrating through the stack structure; forming a groove including a first portion penetrating a portion of the stack structure and a second portion penetrating a portion of the second vertical structure; forming a separation pattern including a first separation portion in the first portion and a second separation portion in the second portion; and performing an oxidation process to oxidize the second vertical structure. The first vertical structure includes a first silicon layer on a side surface of a first insulating pillar, and a second silicon layer on a side surface of a second insulating pillar, and at a first level higher than a lower end of the separation pattern, the second silicon layer includes a first silicon region having a first thickness smaller than a thickness of the first silicon layer.

A semiconductor memory device includes a memory cell array of a three-dimensional structure including a plurality of memory cells repeatedly arranged in a first horizontal direction and a second horizontal direction that are parallel with a main surface of a substrate and cross each other on the substrate and in a vertical direction perpendicular to the main surface, wherein each of the plurality of memory cells includes three transistors. A method of manufacturing a semiconductor memory device includes forming simultaneously a plurality of memory cells arranged in a row in a vertical direction on a substrate, wherein each of the plurality of memory cells includes three transistors.

A method for manufacturing a semiconductor structure and a semiconductor structure are provided. The manufacturing method includes the following operations. A substrate is provided, and a first groove and a second groove are formed in the substrate, each of the first groove and the second groove having a depth in a first direction. The first groove includes multiple first sub-grooves arranged in the first direction, the second groove includes multiple second sub-grooves arranged in the first direction, and sidewalls of the first sub-grooves and sidewalls of the second sub-grooves are convex outwards. Word lines protruding away from the first groove each are formed at an interface of adjacent first sub-grooves. First source-drain layers formed on the sidewalls of the first sub-grooves, and second source-drain layers protruding away from the second groove each are formed at an interface of adjacent second sub-grooves.

Provided are a semiconductor structure and a method for manufacturing the same, a memory device and a method for manufacturing the same. The semiconductor structure includes at least one transistor. Each of the at least one transistor includes a channel including a first semiconductor layer and a second semiconductor layer disposed around the first semiconductor layer. The second semiconductor layer introduces strain into the channel.

Embodiments of the present disclosure relate to the field of semiconductors, and provide a semiconductor structure and a manufacturing method thereof. The semiconductor structure includes: a substrate, including active regions arranged in an array and an isolation structure separating the active regions, where the substrate has a first surface and a second surface opposite to each other; a buried word line structure, located at a side, close to the second surface, in the substrate and embedded in the active regions; a bit line structure, located on the first side of the substrate and electrically connected to the active regions; and capacitor structures, located on the second surface of the substrate and correspondingly connected to the active regions in a one-to-one manner.