An integrated circuit device includes: a substrate including a plurality of active regions; a bit line extending on the substrate in a horizontal direction; a direct contact connected between a first active region selected among the plurality of active regions and the bit line; an inner oxide layer contacting a sidewall of the direct contact; and a carbon-containing oxide layer nonlinearly extending on a sidewall of the bit line in a vertical direction, the carbon-containing oxide layer contacting the sidewall of the bit line.

A method of manufacturing a memory structure is provided. The method includes forming a first gate structure, a second gate structure, and a plurality of source/drain regions in a substrate, in which the plurality of source/drain regions are disposed on opposite sides of the first gate structure and the second gate structures; performing a dry etching process to form a trench between the first gate structure and the second gate structure; performing a wet etching process to expand the trench, in which the expanded trench has a hexagonal shaped cross section profile; and forming a bit line contact in the expanded trench.

The present disclosure relates to a method for preparing a semiconductor device with air gaps between conductive lines (e.g., bit lines). The method includes forming a first dielectric structure and a second dielectric structure over a semiconductor substrate, and forming a conductive material over the first dielectric structure and the second dielectric structure. The conductive material extends into a first opening between the first dielectric structure and the second dielectric structure. The method also includes partially removing the conductive material to form a first bit line and a second bit line in the first opening and forming a sealing dielectric layer over the first bit line and the second bit line such that an air gap is formed between the sealing dielectric layer and the semiconductor substrate.

The present disclosure relates to a semiconductor memory device and a method of fabricating the same, and the semiconductor memory device includes a substrate, an active structure and a shallow trench isolation. The active structure is disposed within the substrate and includes a first active region and a second active region. The first active region includes a plurality of active region units, and the second active region is disposed at an outer side of the first active region to directly connect to a portion of the active region units. The second active region includes a plurality of first openings disposed an edge of the second active region. The shallow trench isolation is disposed within the substrate, to surround the active structure.

Embodiments provide a semiconductor structure and a method for fabricating the same. The semiconductor structure includes: a substrate; bit lines positioned in the substrate, where each of the bit lines includes a conductive body and a dielectric layer, the conductive body includes a body portion and a plurality of contact portions, the body portion extend along a first direction, the contact portions protrude from a side surface of the body portion facing away from a bottom of the substrate, the contact portions are arranged at intervals along the first direction, and the dielectric layer covers side wall surfaces on left and right sides of the body portion along an extension direction; and transistors positioned on top surfaces of the contact portions facing away from the body portion, and extension directions of channels of the transistors are perpendicular to a plane where the substrate is positioned.

Embodiments provide a semiconductor fabrication method. The method includes: providing a substrate including an active layer; and forming a bit line contact layer and a bit line extending along a first direction, two sides of the bit line contact layer being in contact with the active layer and the bit line. Forming the bit line includes: forming a bit line stack including a semiconductor layer and a conductive layer stacked in sequence, the semiconductor layer covering a surface of the substrate and a surface of the bit line contact layer; etching part of the bit line stack to form initial bit lines arranged at intervals, the initial bit lines including a plurality of conductive lines; performing oxidation treatment on the semiconductor layer exposed between adjacent conductive lines to form an oxide layer, the semiconductor layer not oxidized being used as a semiconductor connection layer; and removing the oxide layer.

Embodiments of the present invention provide a method for manufacturing a semiconductor structure, which includes: a base is provided and a stack layer is formed on the base, wherein the stack layer includes at least a first sacrificial layer, and a material of the first sacrificial layer includes an amorphous elemental semiconductor material; second hard mask patterns are formed on the first sacrificial layer through a self-aligned process; a doping process is performed, which includes the operation that a region of the first sacrificial layer exposed from gaps between the second hard mask patterns is doped; the second hard mask patterns are removed; and an undoped region of the first sacrificial layer is removed through a selective etching process so as to form first sacrificial patterns.

The present disclosure provides a method of manufacturing a semiconductor memory and a semiconductor memory, and relates to the technical field of storage devices. The method of manufacturing the semiconductor memory includes: providing a substrate, where multiple active regions arranged at intervals are provided in the substrate; each of the active regions includes a first contact region and second contact regions; forming a bump on each of the second contact regions; forming multiple bit line (BL) structures arranged at intervals on the substrate; forming a first isolation layer covering the BL structures and covering the substrate, where multiple filling holes are provided in the first isolation layer; and forming a wire in each of the filling holes, the wire being electrically connected to the bump.

A semiconductor device includes a plurality of bit line structures formed to be spaced apart from each other over a semiconductor substrate, a first spacer formed on both sidewalls of each of the bit line structures, a lower plug formed between the bit line structures and in contact with the semiconductor substrate, an upper plug positioned over the lower plug and having a greater line width than the lower plug, a middle plug positioned between the lower plug and the upper plug and having a smaller line width than a line width of the lower plug, and a second spacer positioned between the middle plug and the first spacer, wherein the second spacer is thicker than the first spacer.

A semiconductor structure and a method for forming a semiconductor structure are provided. The method includes: a substrate is provided; bit line contact holes spaced apart from each other, bit line contacts each in contact with a part of a respective one of the bit line contact holes, and bit line structures are formed on the substrate, where each of the bit line structures includes at least a conductive layer and an insulating cap layer, and the insulating cap layer is located on the conductive layer; first insulating layers completely filling the bit line contact holes are formed inside the bit line contact holes; and insulation structures with air interlayers are formed on two side walls of the bit line structures, where a height of each of the air interlayers is greater than a height of the conductive layer of each of the bit line structures.