An integrated circuit device including a substrate including a word line trench and a first recess adjacent to a first side wall portion of an inner wall of the word line trench, a channel region on the inner wall and extending in a first direction parallel to an upper surface of the substrate, the channel region including a first channel region in a portion of the substrate adjacent to the inner wall and a second channel region on the inner wall and including a two-dimensional (2D) material of a first conductivity type, a gate insulating layer on the second channel region, a word line on the gate insulating layer and inside the word line trench, and a source region in a first recess and including the 2D material of the first conductivity type may be provided.

A method for forming a semiconductor structure includes: a substrate is provided, in which active areas arranged in a matrix and isolation structures for isolating active areas from each other are formed in substrate, a first direction is a column direction of matrix and a second direction is a row direction of matrix; a conductive layer is formed on substrate; at least conductive layer is etched to form a plurality of bit line grooves extending along first direction and arranged along second direction and a plurality of conductive lines extending along first direction and arranged along second direction; a bit line structure is formed in each bit line groove, in which a gap is formed between bit line structure and each of two sides of a respective one of bit line grooves; and conductive lines are etched along second direction to form conductive pillars serving as storage node contact structures.

Systems, methods and apparatus are provided for an array of vertically stacked memory cells having horizontally oriented access devices and access lines, and shared vertically oriented digit line. The access devices having a first source/drain region and a second source drain region separated by a channel region, and gates opposing the channel region. Horizontal oriented access lines are coupled to the gates and separated from a channel region by a gate dielectric. The memory cells have horizontally oriented storage nodes coupled to the second source/drain region of the horizontally oriented access devices. The shared, vertically oriented digit line is shared between two neighboring horizontal access devices and is coupled to the first source/drain regions of the two neighboring horizontally oriented access devices.

Provided are a vertical-channel cell array transistor structure and a dynamic random-access memory (DRAM) device including the same. The vertical-channel cell array transistor structure includes a semiconductor substrate, a plurality of channels arranged in an array on the semiconductor substrate and each extending perpendicularly from the semiconductor substrate, a gate insulating layer on the plurality of channels, a plurality of word lines on the semiconductor substrate and extending in a first direction, and a two-dimensional (2D) material layer on at least one surface of each of the plurality of word lines.

Present invention relates to a highly-integrated memory cell and a semiconductor device including the same. According to an embodiment of the present invention, a semiconductor device comprises: an active layer including a channel, the active layer being spaced apart from a substrate and extending in a direction parallel to a surface of the substrate; a gate dielectric layer formed over the active layer; a word line laterally oriented in a direction crossing the active layer over the gate dielectric layer and including a low work function electrode and a high work function electrode, the high work function electrode having a higher work function than the low work function electrode; and a dipole inducing layer disposed between the high work function electrode and the gate dielectric layer.

The embodiments of the disclosure provide a method for forming a semiconductor structure and a semiconductor structure. The method includes that: a base is provided, in which the base includes a Word Line (WL) trench with a stepped side wall, and a width of a top of the WL trench is greater than a width of a bottom of the WL trench; an insulating structure is formed on the side wall and the bottom wall of the WL trench; and a WL structure is formed in the WL trench where the insulating structure is formed.

Apparatuses and methods to provide a patterned substrate are described. A plurality of patterned and spaced first lines and carbon material lines and formed on the substrate surface by selectively depositing and etching films extending in a first direction and films extending in a second direction that crosses the first direction to pattern the underlying structures.

Electronic devices and methods of forming electronic devices using a reduced number of hardmask materials and reusing lithography reticles are described. Patterned substrates are formed using a combination of etch selective hardmask materials and reusing reticles to provide a pattern of repeating trapezoidal and rhomboidal openings.

Disclosed is a semiconductor device for improving a gate induced drain leakage and a method for fabricating the same, and the semiconductor device includes a substrate, a first doped region and a second doped region formed to be spaced apart from each other by a trench in the substrate, a first gate dielectric layer over the trench, a lower gate over the first gate dielectric layer, an upper gate over the lower gate and having a smaller width than the lower gate, and a second gate dielectric layer between the upper gate and the first gate dielectric layer.

A semiconductor memory device is disclosed. The device may include first and second impurity regions provided in a substrate and spaced apart from each other, the second impurity region having a top surface higher than the first impurity region, a device isolation pattern interposed between the first and second impurity regions, a first contact plug, which is in contact with the first impurity region and has a bottom surface lower than the top surface of the second impurity region, a gap-fill insulating pattern interposed between the first contact plug and the second impurity region, a first protection spacer interposed between the gap-fill insulating pattern and the second impurity region, and a first spacer, which is in contact with a side surface of the first contact plug and the device isolation pattern and is interposed between the first protection spacer and the gap-fill insulating pattern.