Disclosed are DRAM devices and methods of forming DRAM devices. One method may include forming a plurality of trenches and angled structures, each angled structure including a first sidewall opposite a second sidewall, wherein the second sidewall extends over an adjacent trench. The method may include forming a spacer along a bottom surface of the trench, along the second sidewall, and along the first sidewall, wherein the spacer has an opening at a bottom portion of the first sidewall. The method may include forming a drain in each of the angled structures by performing an ion implant, which impacts the first sidewall through the opening at the bottom portion of the first sidewall. The method may include removing the spacer from the first sidewall, forming a bitline over the spacer along the bottom surface of each of the trenches, and forming a series of wordlines along the angled structures.

A semiconductor device includes a semiconductor substrate and word line structures. A plurality of active areas are formed in the substrate, and the plurality of active areas are isolated by an isolation structure. The isolation structure includes first areas and second areas. A dimension of the second areas is larger than that of the first areas in first direction. The word line structures are below a surface of the substrate and extend in first direction. The word line structures penetrate the isolation structure and the plurality of active areas. A word line structure includes first sub-word line structures located in first areas and second sub-word line structures located in second areas. The first sub-word line structures have first dimension in second direction, and the second sub-word line structures have second dimension at least larger than first dimension in second direction. The second direction forms an included angle with first direction.

Embodiments relate to a semiconductor structure and a method for fabricating. The semiconductor structure includes: a substrate, word lines, bit lines, and word line isolation structures. Active pillars arranged in an array are provided on a surface of the substrate, and the active pillars include channel regions, and a top doped region positioned on an upper side of the channel region and a bottom doped region positioned on a lower side of the channel region. The word lines extend along a first direction and surround the channel regions of a row of the active pillars arranged along the first direction. The bit lines extend along a second direction and are electrically connected to the bottom doped regions of a column of the active pillars arranged along the second direction, and in a direction facing away from the surface of the substrate.

A word line driver includes a PMOS area, a NMOS area, first gates, and second gates. The PMOS area includes first active areas extending along a first direction. The first active area includes a first channel area, a first source area and a first drain area. The NMOS area includes second active areas. The second active area includes a second channel area, a second source area, a second drain area, a third channel area, a third source area, and a third drain area. The extension direction of the first gate corresponding to the first active area is inclined compared with the first direction. The second gate covers the third channel area. The second gate, the third source area and the third drain area constitute a holding transistor.

A method for forming a transistor structure includes steps as follows: A substrate with an original surface is prepared. Next a gate conductive region is formed, wherein at least a portion of the gate conductive region is disposed below the original surface, and a bottom wall and sidewalls of the gate conductive region is surrounded by a gate dielectric layer. Then, a first conductive region is formed, wherein a bottom wall of the first conductive region is aligned or substantially aligned with a top wall of the gate conductive region.

A preparation method for a semiconductor structure includes the following operations. A bit line structure, active pillars, and a word line structure are formed in turn on a substrate. Bottom ends of the active pillars are connected to the bit line structure, and the active pillars are connected with the word line structure. A pillar-shaped conductive structure is formed on the active pillars, and a cup-shaped conductive structure is formed on the pillar-shaped conductive structure. There is an electrode gap between the pillar-shaped conductive structure and the cup-shaped conductive structure, and the pillar-shaped conductive structure and the cup-shaped conductive structure form a lower electrode. A dielectric layer is formed on a surface of the lower electrode. An upper electrode is formed on a surface of the dielectric layer. The upper electrode fills the electrode gap.

A semiconductor memory device includes a substrate, an active structure, a shallow trench isolation and a plurality of word lines. The active structure is disposed in the substrate, and includes a plurality of first active fragments and a plurality of second active fragments extended parallel to each other along a first direction and the second active fragments are disposed outside a periphery of all of the first active fragments. The shallow trench isolation is disposed in the substrate to surround the active structure, and which includes a plurality of first portions and a plurality of second portions. The word lines are disposed in the substrate, parallel with each other to extend along a second direction, wherein at least one of the word lines are only intersected with the second active fragments, or at least one of the word lines does not pass through any one of the second portions.

The present application discloses method for fabricating a conductive feature and a method for fabricating a semiconductor device. The method includes providing a substrate; forming a recess in the substrate; conformally forming a first nucleation layer in the recess; performing a post-treatment to the first nucleation layer; and forming a first bulk layer on the first nucleation layer to fill the recess. The first nucleation layer and the first bulk layer configure the conductive feature. The first nucleation layer and the first bulk layer include tungsten. The post-treatment includes a borane-containing reducing agent.

Embodiments provide a semiconductor structure and a fabrication method. The method includes: providing a substrate provided with first trenches and including an active pillar positioned between adjacent two of the first trenches; forming, in the active pillar, a second trench whose bottom is greater than or equal to a bottom of the first trench in height; forming a first dielectric layer and a protective layer in the first trench, the first dielectric layer being positioned between the protective layer and the active pillar, and an upper surface of the first dielectric layer being lower than an upper surface of the active pillar; forming second dielectric layers on an exposed side wall of the first trench and a side wall of the second trench, a third trench being formed between each of the second dielectric layers and the protective layer, and a fourth trench being formed between the second dielectric layers.

A semiconductor device includes: an active region defined by a device isolation layer formed in a substrate; a word line configured to cross the active region, the word line extending in a first direction and being formed in the substrate; a bit line extending in a second direction perpendicular to the first direction on the word line; a first contact connecting the bit line to the active region; a first mask for forming the active region, the first mask being formed on the active region; and a second mask of which a height of a top surface thereof is greater than a height of a top surface of the active region, the second mask covering the word line, wherein the active region has a bar shape that extends to form an acute angle with respect to the first direction.