Embodiments relate to a semiconductor device, including a channel area; a gate line extending along the channel area so that the channel area can be set into a conductive state by activating the gate line; a plurality of terminals including an electrical connection to the channel area, so that the plurality of terminals is connectable to a predetermined voltage by activating the gate line.

A memory device that includes a plurality of ROM cells each having spaced apart source and drain regions formed in a substrate with a channel region therebetween, a first gate disposed over and insulated from a first portion of the channel region, a second gate disposed over and insulated from a second portion of the channel region, and a conductive line extending over the plurality of ROM cells. The conductive line is electrically coupled to the drain regions of a first subgroup of the ROM cells, and is not electrically coupled to the drain regions of a second subgroup of the ROM cells. Alternately, a first subgroup of the ROM cells each includes a higher voltage threshold implant region in the channel region, whereas a second subgroup of the ROM cells each lack any higher voltage threshold implant region in the channel region.

A small-area high-efficiency read-only memory (ROM) array and a method for operating the same are provided. The small-area high-efficiency ROM array includes bit lines, word common-source lines, and sub-memory arrays. Each sub-memory array includes first, second, third, and fourth memory cells connected to a bit line and a word common-source line. All the memory cells are connected to the same word common-source line and respectively connected to different bit lines. Sharing the gate and the source can not only greatly reduce the overall layout area, but also effectively reduce the load of the memory array to achieve the high-efficiency reading and writing goal.

In a semiconductor storage device, a first ROM cell includes a first nanosheet FET having a first nanosheet as the channel region, provided between a first bit line and a first ground power supply line. A second ROM cell includes a second nanosheet FET having a second nanosheet as the channel region, provided between a second bit line and a second ground power supply line. The face of the first nanosheet closer to the second nanosheet in the X direction is exposed from a first gate interconnect, and the face of the second nanosheet closer to the first nanosheet in the X direction is exposed from a second gate interconnect.

A ROM cell includes first and second three-dimensional transistors. The second transistor is formed above the first transistor, and the channel portions of the first and second transistors overlap each other. First data is stored depending on whether first and second local interconnects connected to the nodes of the first transistor are connected to a same line, or different lines, out of a bit line and a ground power supply line. Second data is stored depending on whether third and fourth local interconnects connected to the nodes of the second transistor are connected to a same line, or different lines, out of a bit line and a ground power supply line.

A ROM cell using a complementary FET (CFET) includes: a first three-dimensional transistor provided between a first bit line and a first ground power supply line, and a second three-dimensional transistor provided between a second bit line and a second ground power supply line. Channel portions of the first and second transistors overlap each other in planar view. First data is stored depending on the presence or absence of connection between the source of the first transistor and the first ground power supply line. Second data is stored depending on the presence or absence of connection between the source of the second transistor and the second ground power supply line. The first and second bit lines are formed in a buried interconnect layer.

A memory circuit includes first and second memory cells aligned along a first active structure including a first shared source portion of the first and second memory cells, third and fourth memory cells aligned along a second active structure including a second shared source portion of the third and fourth memory cells, a first bit line overlying the first and second memory cells, a second bit line overlying the third and fourth memory cells, a reference voltage line positioned in a same metal layer as the first and second bit lines, and a first conductive structure electrically connected to each of the first and second shared source portions and the reference voltage line. The first conductive structure is positioned in a metal layer different from the same metal layer.

A layout structure of a ROM cell using a complementary FET (CFET) is provided. The ROM cell includes first and second three-dimensional transistors. The second transistor is formed above the first transistor, and the channel portions of the first and second transistors overlap each other. First data is stored in the ROM cell depending on the presence or absence of connection between a local interconnect connected to the source of the first transistor and a ground power supply line, and second data is stored in the ROM cell depending on the presence or absence of connection between a local interconnect connected to the source of the second transistor and a ground power supply line.

Various implementations described herein are related to a device including a bitcell having a bitcell layout with a first metal layer, a second metal layer and a via programming layer. The device may have a via marking layer provided in the bitcell layout for the bitcell, and the via marking layer controls optical proximity correction of the first metal layer and the second metal layer.

A memory array includes a continuous active region extending along a direction. The memory array includes a first bit cell, which includes a first programming device and a pair of first reading devices defined on the continuous active region. The memory array includes a first programing word line coupled to a gate of the first programing device. The memory array includes a first reading word line coupled to gates of the pair of first reading devices. The memory array includes a bit line, wherein a first one of the pair of first reading devices is coupled between a first source/drain node of the first programing device and the bit line.