A read-only memory (ROM) device includes a complementary field effect transistor (CFET) device which has a first semiconductor device of a first type, and a second semiconductor device of a second type different from the first type. The second semiconductor device is under the first semiconductor device. A first word line is electrically coupled to a gate of the first semiconductor device. A second word line is electrically coupled to a gate of the second semiconductor device. The first semiconductor device is configured to store a first logic value. The second semiconductor device is configured to store a second logic value, independently of the first logic value stored in the first semiconductor device.

A method of manufacturing an IC device includes forming same length first through fourth gate structures, the first and second gate structures overlapping first through fourth active areas, and free of overlapping fifth and sixth active areas, and the third and fourth gate structures overlapping the third through sixth active areas, and free of overlapping the first and second active areas; forming MD segments; forming a dummy array connection, including: forming a frontside via structure on an MD segment of the fifth and sixth active areas, or forming a backside via structure on the fifth and sixth active areas; and forming frontside and backside metal lines, the forming a dummy array connection further including at least one of: connecting frontside metal lines to frontside via structures of the fifth and sixth active areas, or connecting backside metal lines to backside via structures of the fifth and sixth active areas.

A IC device manufacturing method includes: forming first through sixth active areas; forming first through fourth gate structures, wherein: the first through fourth gate structures have a same length, and each of the first through fourth gate structures has a first end, a second end opposite to the first end, and is continuously conductive from the first to second end; forming a first isolation structure abutting first ends of the first and second gate structures; forming a second isolation structure abutting second ends of the first and second gate structures; and forming a third isolation structure abutting first ends of the third and fourth gate structures, wherein: the third isolation structure is between the first and second isolation structures, the third isolation structure is spaced from the first isolation structure by a first distance, and the third isolation structure is spaced from the second isolation structure by the first distance.

A nanosheet 1T-4R mask programed multi-level read-only memory component includes a plurality of nanosheet channels between a first source/drain and a second source/drain and a gate around the plurality of nanosheet channels. The component includes a first resistor upon a frontside surface of the first source/drain, a second resistor upon a frontside surface of the second source/drain, a third resistor upon a backside surface of the first source/drain, and a fourth resistor upon a backside surface of the second source/drain. Respective frontside contacts electrically connect the first resistor, the second resistor, and the gate to a frontside backend of line (BEOL) network. Respective backside contacts electrically connect the third resistor and the fourth resistor to a backside power delivery network (BSPDN).

Various implementations described herein are related to a device having a memory architecture with a multi-stack of transistors that may be arranged in a multi-bitcell stack configuration. Also, the memory architecture may have a wordline that may be shared across the transistors of the multi-stack of transistors with each transistor coupled to a different bitline.